LXT970A 데이터 시트보기 (PDF) - Intel
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LXT970A Datasheet PDF : 74 Pages
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Dual-Speed Fast Ethernet Transceiver — LXT970A
and an optional interrupt line (MDINT). The LXT970A can signal an interrupt using the MDIO
signal as shown in Figure 8. The user can also assign a separate pin for this function. If bit 17.1 = 1,
pin 2 (FDS/MDINT) will be used as an MDINT pin.
The protocol allows one controller to communicate with multiple LXT970A devices. The MF pins
control one bit each of the 5-bit address setting. Each LXT970A is assigned an MII address
between 0 and 31. Details of the MF inputs are shown in Table 7 on page 14. Timing for the MDIO
Interface is shown in Table 42 on page 61. Read and write operations are shown in Figure 9 and
Figure 10. Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High,
the MDIO operates as a read-only interface. When MDDIS is Low, read and write are enabled.
The LXT970A supports twelve 16-bit MDIO registers. Registers 0-6 are required and their
functions are specified by the IEEE 802.3 specification. Additional registers are included for
expanded functionality. The MDIO Register set for the LXT970A is described in Table 45 through
Table 56. Specific bits in the registers are referenced using an “X.Y” notation, where X is the
register number (0-6 or 16-20) and Y is the bit number (0-15).
MII Management Interrupt
The MDINT/FDS pin functions as a management data interrupt on the MII when 17.1 = 1. An
active Low on this pin indicates a status change on the LXT970A. The interrupt is activated when
changes are made to the following conditions:
• Link Status
• Duplex Status
This interrupt is cleared by sequentially reading Register 1 and Register 18.
Figure 8. MDIO Interrupt Signaling
MDC
MDIO
Interrupt
Z0
Turn
Around
MDIO FRAME
Read Data
Sourced by
LXT970A
INT
Idle
Figure 9. Management Interface - Read Frame Structure
MDC
MDIO
(Read)
32 "1"s
0
1
1
0
A4
A3
A0
R4
R3
R0
Z0
D15 D15D14 D14 D1 D1 D0
Idle Preamble
SFD
Op Code
PHY Address
Register Address
Turn
Around
Data
Idle
Write
Read
Figure 10. Management Interface - Write Frame Structure
MDC
MDIO
(Write)
32 "1"s
0
1
0
1
A4
A3
A0
R4
R3
R0
1
0
D15
D14
D1
D0
Idle Preamble
SFD
Op Code
PHY Address
Register Address
Turn
Around
Data
Idle
Write
Datasheet
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