LXT970A 데이터 시트보기 (PDF) - Intel

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LXT970A

Dual-Speed Fast Ethernet Transceiver

Intel 

Dual-Speed Fast Ethernet Transceiver — LXT970A

Table 14. LXT970A Operating Configurations / Auto-Negotiation Disabled

Desired Configuration1,2

Pin Name

Input Value

MDIO Registers

Force 100FX Operation

MF4

VMF2, VMF3

CFG0

High

MF3

VMF1, VMF4

Force 100TX Operation

MF4

CFG0

VMF1, VMF4

High

Force 10T Operation

MF4

CFG0

VMF1, VMF4

Low

Force Full-Duplex Operation

FDE

High

Disable 10T Link Test

CFG1

High

Enable 10T Link Test

CFG1

Low

1. Refer to Table 12 for basic configurations.

2. Refer to Table 13 for Hardware Control Interface functions available when auto-negotiation is enabled.

19.2 = 1

0.13 = 1

19.3 = 0

19.2 = 0

0.13 = 1

19.2 = 0

0.13 = 0

0.8 = 1

19.8 = 1

19.8 = 0

2.3

2.3.1

2.3.1.1

2.3.2

Operating Requirements

Power Supply Requirements

The LXT970A requires a 5V power supply. Power should be supplied from a single source to the

VCC, VCCA, VCCT, and VCCR power pins. A ground return path must be provided to the GND,

GNDA, GNDT, and GNDR pins. As a matter of practice, the power supply should be as clean as

possible. Filtering is recommended for the analog power pins (VCCA, VCCT, VCCR) at least in

the initial design. Consult the Design Recommendations section on page 42 for details. A

decoupling capacitor is recommended between each VCC pin and its respective GND, placed as

close to the device as possible.

Optional MII Power Supply

The MII may be powered by either a 3.3V or 5V source via the VCCIO pin. To avoid power

sequencing issues, the VCCIO pin should be supplied from the same source used to power the

other side of the MII interface. When VCCIO is supplied with 3.3V, the MII inputs are not tolerant

of 5V signal levels. The MDIO and MDC pins must be operated at the same voltage as the rest of

the MII interface.

Reference Clock Requirements

The LXT970A requires a continuous, stable reference clock. There are two clock modes, Master

Clock Mode and Slave Clock Mode. Depending on the mode of operation, the clock may be

supplied at the crystal oscillator pins (XI, XO), or at the Transmit Clock pin (TX_CLK). See Table

25 on page 48 for input clock requirements.

Datasheet

27

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