M95512-DR 데이터 시트보기 (PDF) - STMicroelectronics

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M95512-DR

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Operating features

M95512-W, M95512-R

4.4

Status register

Figure 7 shows the position of the Status register in the control logic of the device. The

Status register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a

detailed description of the Status register bits

4.5

Data protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and

within applications that could experience problems if memory bytes are corrupted.

Consequently, the device features the following data protection mechanisms:

● Write and Write Status register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

● All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

– Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Write (WRITE) instruction completion

● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be

configured as read-only.

● The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the

Status Register.

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after

the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

● The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

● The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2.

Write-protected block size

Status register bits

BP1

BP0

0

0

0

1

1

0

1

1

Protected block

none

Upper quarter

Upper half

Whole memory

Protected array

addresses

none

C000h - FFFFh

8000h - FFFFh

0000h - FFFFh

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Doc ID 11124 Rev 13

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