M95512-DR 데이터 시트보기 (PDF) - STMicroelectronics

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M95512-DR

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

M95512-W, M95512-R

Instructions

Table 6. Protection modes

W SRWD

Signal Bit

Mode

Write Protection of the

Status Register

Memory content

Protected area(1) Unprotected area(1)

1

0

Status Register is Writable

0

1

0

Software (if the WREN instruction

Protected has set the WEL bit)

Write Protected

1

(SPM) The values in the BP1 and

BP0 bits can be changed

Ready to accept

Write instructions

Status Register is

0

Hardware Hardware write protected

1 Protected The values in the BP1 and Write Protected

(HPM) BP0 bits cannot be

Ready to accept

Write instructions

changed

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

The protection features of the device are summarized in Table 6.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register (provided that the WEL bit has

previously been set by a WREN instruction), regardless of the logic level applied on the

Write Protect (W) input pin.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W) input pin:

● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided

that the WEL bit has previously been set by a WREN instruction.

● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the WEL bit has previously been set by a WREN instruction (attempts to write to the

Status Register are rejected, and are not accepted for execution). As a consequence,

all the data bytes in the memory area that are software-protected (SPM) by the Block

Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against

data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

entered either:

● by setting the SRWD bit after driving the Write Protect (W) input pin low

● or by driving the Write Protect (W) input pin low after setting the SRWD bit

Once entered, the Hardware-protected mode (HPM) can only be exited by pulling Write

Protect (W) high.

If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can

never be activated, and only the Software-protected mode (SPM) using the Block Protect

(BP1, BP0) bits in the Status Register, can be used.

Doc ID 11124 Rev 13

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