M95512-DR 데이터 시트보기 (PDF) - STMicroelectronics

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M95512-DR

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

M95512-W, M95512-R

Instructions

6.6

Note:

Write to Memory Array (WRITE)

As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte, address byte, and at least one data byte are then shifted

in, on Serial Data Input (D).

The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input

data. The self-timed Write cycle triggered by the rising edge of Chip Select (S) continues for

a period tW (as specified in Table 16 and Table 18), at the end of which the Write in Progress

(WIP) bit is reset to 0.

In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte

has been latched in, indicating that the instruction is being used to write a single byte. If,

though, Chip Select (S) continues to be driven low, as shown in Figure 14., the next byte of

input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address

counter are incremented. If the number of data bytes sent to the device exceeds the page

boundary, the internal address counter rolls over to the beginning of the page, and the

previous data there are overwritten with the incoming data. (The page size of these devices

is 128 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

● if a Write cycle is already in progress

● if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in)

● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

The self-timed write cycle tW is internally executed as a sequence of two consecutive

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is

read as “0” and a programmed bit is read as “1”.

Figure 13. Byte Write (WRITE) sequence

S

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

C

Instruction

16-Bit Address

Data Byte

D

15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

High Impedance

Q

AI01795D

Doc ID 11124 Rev 13

23/48

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