SC220 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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SC220

XpressFlow Engine XpressFlow 2020 Ethernet Routing Switch Chipset

Zarlink Semiconductor Inc 

PRELIMINARY

XpressFlow-2020 Series –

Ethernet Switch Chipset

INFORMATION

SC220

XpressFlow Engine

Supported Memory Configurations

Read/Write Chip Select and High Address Bits

RAM

Chip Size

# of

RAM

Chips

Chip #3

Chip #2

Chip #1

Chip #0

Total Buffer

Memory

L_A[19] /

L_WE[3]#

L_OE[3]#

L_WE[2]#

L_OE[2]#

L_WE[1]#

L_OE[1]#

L_WE[0]#

L_OE[0]#

Size

64k x 32 1 256k bytes ----

----

----

----

----

---- L_WE[0]# L_OE[0]#

2 512k bytes ----

----

----

---- L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#

4 1M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#

128k x 32 1

2

4

256k bytes ----

----

----

----

----

---- L_WE[0]# L_OE[0]#

1M bytes ----

----

----

---- L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#

2M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#

256k x32 1 1M bytes L_A[19] ----

----

----

----

---- L_WE[0]# L_OE[0]#

2 2M bytes L_A[19] ----

----

---- L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#

2.2.2 Bus Cycle Waveforms

L_CLK

L_ADSC#

L_CS#

L_A[19:2]

L_WE[3:0]#

A1

A2

A3

A3+1 A3+2 A3+3

A4 A4+1 A4+2 A4+3

A5

L_BWE[3:0]#

L_OE[3:0]#

L_D[31:0] (Wr)

D1

D3 D3+1 D3+2 D3+3

L_D[31:0] (Rd)

D2

D4 D4+1 D4+2 D4+3

Typical Local Memory Access Operations

Note: Refer to manufacturer’s data sheet for detailed timing parameters.

A6

D6

D5

© 1998 Vertex Networks, Inc.

14

1999

Rev. 4.5 – February

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