SC220 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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SC220 Datasheet PDF : 34 Pages
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PRELIMINARY
XpressFlow-2020 Series –
Ethernet Switch Chipset
INFORMATION
SC220
XpressFlow Engine
2.3.5 Register Map
Note:
All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a
single operation.
These registers are reserved for system diagnostic usage only.
I/O Offset
Register Description
Little Big Reg.
Endian Endian Size
Device Configuration Registers (DCR)
GCR Global Control Register
DCR0 Device Status Register
DCR1 Signature & Revision Register
hF00
hF00
hF10
hF02
hF02
hF12
16-bit
16-bit
16-bit
DCR2
DCR3
DCR4
DCR5
ID Register
Local Control Register
Interface Status Register
Bus Credit Register
hF20
hF30
hF40
hF50
hF22
hF32
hF42
hF52
16-bit
16-bit
16-bit
16-bit
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
ISRM Interrupt Status Register – Masked
hF80 hF82 16-bit
hF90 hF92 16-bit
IMSK
IAR
Interrupt Mask Register
Interrupt Acknowledgment Register
hFA0 hFA2 16-bit
hFB0 hFB2 16-bit
Buffer Memory Interface
MWAR Memory Write Address Register – Single Cycle
MRAR Memory Read Address Register – Single Cycle
MBAR Memory Address Register – Burst Mode
MWBS Memory Write Burst Size (in D-words)
hE08
hE18
hE28
hE40
hE08
hE18
hE28
hE42
32-bit
32-bit
32-bit
16-bit
MRBS
MWDR
MWDX
MRDR
MRDX
Memory Read Burst Size (in D-words)
Memory Write Data Register
Memory Write Data Register – Byte Swapping
Memory Read Data Register
Memory Read Data Register – Byte Swapping
hE50
hE68
hE6C
hE68
hE6C
hE52
hE68
hE6C
hE68
hE6C
16-bit
32-bit
32-bit
32-bit
32-bit
Buffers & Stacks Management
Frame Control Buffers
FCBBA Frame Control Buffer – Base Address
FCBA Frame Control Buffer – Buffer Allocation
FCBR Frame Control Buffer – Buffer Release
FCBAG Frame Control Buffer – Buffer Aging Status
hD00
hD20
hD20
hD30
hD02
hD22
hD22
hD32
16-bit
16-bit
16-bit
16-bit
FCBSA
FCBSL
FCBST
FCBSS
Frame Ctrl Buffer Stack – Base Address
Frame Ctrl Buffer Stack – Size Limit
Frame Ctrl Buffer Stack – Buffer Low Threshold
Frame Ctrl Buffer Stack – Allocation Status
hD80
hD90
hDA0
hDB0
hD82
hD92
hDA2
hDB2
16-bit
16-bit
16-bit
16-bit
W/R
W/--
--/R
--/R
W/R
W/R
--/R
W/R
--/R
--/R
W/R
W/--
W/R
W/R
W/R
W/R
W/R
W/--
W/--
--/R
--/R
W/R
--/R
W/--
--/R
W/R
W/R
W/R
--/R
Note:
© 1998 Vertex Networks, Inc.
18
1999
Rev. 4.5 – February
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