AB28F800BR-B80 데이터 시트보기 (PDF) - Intel

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AB28F800BR-B80

2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

E

CUI will respond to status reads and erase

suspend. After the WSM has completed its task, it

will set the WSM Status bit to a “1,” which will also

allow the CUI to respond to its full command set.

Note that after the WSM has returned control to the

CUI, the CUI will stay in the current command state

until it receives another command.

3.3.1.1

Command Function Description

Device operations are selected by writing specific

commands into the CUI. Table 5 defines the

available commands.

Table 5. Command Set Codes and

Corresponding Device Mode

Command Codes

Device Mode

00

Invalid Reserved

10

Alternate Program Set-

Up

20

Erase Set-Up

40

Program Set-Up

50

Clear Status Register

70

Read Status Register

90

Intelligent Identifier

B0

Erase Suspend

D0

Erase Resume/Erase

Confirm

FF

Read Array

Invalid/Reserved

These are unassigned commands and should not

be used. Intel reserves the right to redefine these

codes for future functions.

Read Array (FFH)

This single write cycle command points the read

path at the array. If the host CPU performs a

CE#/OE#-controlled Read immediately following a

two-write sequence that started the WSM, then the

device will output Status Register contents. If the

A28F200BR

Read Array command is given after the Erase

Setup command, the device will reset to read the

array. A two Read Array command sequence (FFH)

is required to reset to Read Array after the Program

Setup command.

Intelligent Identifier (90H)

After this command is executed, the CUI points the

output path to the intelligent identifier circuits. Only

intelligent identifier values at addresses 0 and 1 can

be read (only address A0 is used in this mode, all

other address inputs are ignored).

Read Status Register (70H)

This is one of the two commands that is executable

while the WSM is operating. After this command is

written, a read of the device will output the contents

of the Status Register, regardless of the address

presented to the device.

The device automatically enters this mode after

program or erase has completed.

Clear Status Register (50H)

The WSM can only set the Program Status and

Erase Status bits in the Status Register to “1,” it

cannot clear them to “0.”

Two reasons exist for operating the Status Register

in this fashion. The first is synchronization. Since

the WSM does not know when the host CPU has

read the Status Register, it would not know when to

clear the status bits. Secondly, if the CPU is

programming a string of bytes, it may be more

efficient to query the Status Register after

programming the string. Thus, if any errors exist

while programming the string, the Status Register

will return the accumulated error status.

Program Setup (40H or 10H)

This command simply sets the CUI into a state

such that the next write will load the Address and

Data registers. After this command is executed, the

outputs default to the Status Register. A two Read

Array command sequence (FFH) is required to

reset to Read Array after the Program Setup

command.

ADVANCE INFORMATION

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