AB28F800BR-B80 데이터 시트보기 (PDF) - Intel
부품명
상세내역
제조사
AB28F800BR-B80 Datasheet PDF : 36 Pages
| |||
E
A28F200BR
Start
Write 20H,
Block Address
Write D0H and
Block Address
Read Status
Register
0
SR.7 =
Suspend Erase
Loop
NO
Suspend YES
Erase
1
Full Status
Check if Desired
Bus
Operation
Write
Write
Read
Command
Comments
Erase Setup
Erase
Confirm
Data = 20H
Addr = Within Block to be Erased
Data = D0H
Addr = Within Block to be Erased
Status Register Data
Toggle CE# or OE#
to Update Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase,
or after a sequence of block erasures.
Write FFH after the last operation to reset device to read
array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
0
1
SR.4,5 =
0
1
SR.5 =
0
Block Erase
Successful
VPP Range Error
Command Sequence
Error
Block Erase
Error
Bus
Operation
Standby
Standby
Standby
Command
Comments
Check SR.3
1 = VPP Low Detect
Check SR.4,5
Both 1 = Command
Sequence Error
Check SR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.5 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0542_05
Figure 5. Automated Block Erase Flowchart
ADVANCE INFORMATION
19
Share Link: 