AB28F400BR-B80 데이터 시트보기 (PDF) - Intel

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AB28F400BR-B80

2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

A28F200BR

E

Start

Write B0H

Read

Status Register

0

SR.7 =

1

0

CSR.6 =

1

Write FFH

Read Array Data

Erase Completed

Bus

Operation

Write

Read

Standby

Standby

Write

Read

Write

Command

Comments

Erase

Suspend

Read Array

Data = B0H

Addr = X

Status Register Data

Toggle CE# or OE#

to update SRD.

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Check SR.6

1 = Erase Suspended

0 = Erase Completed

Data = FFH

Addr = X

Read array data from block other

than the one being erased.

Erase Resume Data = D0H

Addr = X

Done

NO

Reading

YES

Write D0H

Write FFH

Erase Resumed

Read Array Data

0542_06

Figure 6. Erase Suspend/Resume Flowchart

3.4 Boot Block Locking

The boot block family architecture features a

hardware-lockable boot block so that the kernel

code for the system can be kept secure while the

parameter and main blocks are programmed and

erased independently as necessary. Only the boot

block can be locked independently from the other

blocks.

3.4.1

VPP = VIL FOR COMPLETE

PROTECTION

For complete write protection of all blocks in the

flash device, the VPP programming voltage can be

held low. When VPP is below VPPLK, any program or

erase operation will result in a error in the Status

Register.

20

ADVANCE INFORMATION

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