29104BJA 데이터 시트보기 (PDF) - Intersil
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29104BJA Datasheet PDF : 7 Pages
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Timing Waveforms (Continued)
HM-65162
ADDRESS
G
E
W
Q
D
(10) TAVAX
(22) TAVWH
(11) TELWH
(14)
TWHAX
(12) TAVWL
(13) TWLWH
TGHQZ
(15)
(21) TDVEH
(17) TDVWH
(18) TWHDX
FIGURE 3. WRITE CYCLE II
In this write cycle G has control of the output after a period, allows data in to be applied without bus contention after
TGHQZ. G switching the output to a high impedance state
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention;
within VCC -0.3V to VCC +0.3V.
2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high im-
pedance, minimizing power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept be-
tween VCC +0.3V and 70% of VCC during the power up
and down transitions.
4. The RAM can begin operation > 55ns after VCC reaches
the minimum operating voltage (4.5V).
VCC
E
4.5V
DATA
RETENTION
TIMING
VCC ≥ 02.0V
VCC -0.3V TO VCC +0.3V
4.5V
>55ns
FIGURE 4. DATA RETENTION TIMING
6
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