87C524 데이터 시트보기 (PDF) - Philips Electronics
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87C524 Datasheet PDF : 26 Pages
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Philips Semiconductors
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
Product specification
87C524/87C528
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
VDD and RST must come up at the same time for a proper start-up.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
The power-down mode can be terminated by a RESET in the same
way as in the 80C51 or in addition by one of two external interrupts,
INT0 or INT1. A termination with an external interrupt does not affect
the internal data memory and does not affect the special function
registers. This makes it possible to exit power-down without
changing the port output levels. To terminate the power-down mode
with an external interrupt INT0 or INT1 must be switched to
level-sensitive and must be enabled. The external interrupt input
signal INT0 and INT1 must be kept low until the oscillator has
restarted and stabilized. An instruction following the instruction that
puts the device in the power-down mode will be executed. A reset
generated by the watchdog timer terminates the power-down mode
in the same way as an external RESET, and only the contents of the
on-chip RAM are preserved. The control bits for the reduced power
modes are in the special function register PCON.
DESIGN CONSIDERATIONS
At power-on, the voltage on VDD and RST must come up at the
same time for a proper start-up.
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write when idle is terminated by reset, the instruction
following the one that invokes idle should not be one that writes to a
port pin or to external memory.
Table 5 shows the state of I/O ports during low current operating
modes.
Table 5. External Pin Status During Idle and Power-Down Modes
MODE
Idle
PROGRAM MEMORY
Internal
ALE
1
PSEN
1
PORT 0
Data
Idle
External
1
1
Float
Power-down
Internal
0
0
Data
Power-down
External
0
0
Float
PORT 1
Data
Data
Data
Data
PORT 2
Data
Address
Data
Data
PORT 3
Data
Data
Data
Data
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER
RATING
UNIT
Operating temperature under bias
0 to +70, or
–40 to +85
°C
Storage temperature range
–65 to +150
°C
Voltage on any other pin to VSS
Input, output current on any two pins
–0.5 to VDD +0.5
V
±10
mA
Power dissipation
(based on package heat transfer limitations, not device power consumption)
1.0
W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1999 Jul 23
10
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