AD7570 데이터 시트보기 (PDF) - Analog Devices

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AD7570

CMOS 10-Bit Monolithic A/D Converter

Analog Devices 

APPLICA nONS

OPTIMIZED LAYOUT

~~

AD7570-t

'j i ~ ..

t

oun

Ik LOAD

-~

NOTES:

1. ALL PC TRACES ON BOTTOM OF BOARD.

O . 2. LAYOUT SHOWN TERMINATES oun

IVREF -JOY. AIN' 0 TO +IOV).

INTO

+ INPUT

OF AD311

TYPE

COMPARATOR.

B Figure 13. PC Layout (Top View)

S BUSING MULTIPLE AD7570 OUTPUTS

O Several AD7570's may be paralleled to a data bus to provide

L an AID converter per analog channel, this providing increased

E system throughput rate. For example, Figure 14 shows such

TE a system for 12 AD7570's in parallel.

available at the AID output only after conversion is complete,

and until another "convert start" is initiated. The timing

diagram of Figure 15 illustrates how the STRT signals of the

twelve AD7570's might be staggered to provide a total system

throughput twelve times as great as the classic method of data

t

t

The three-state output logic enables of each AD7570 is con-

acquisition (an analog multiplexer feeding multichannel analog

trolled by its own BUSY (status) outputs. Thus, data is

data to a single AID converter).

STRT 1

BSEN1

AIN 1

CLK 0

VREF

STRT12

BSEN 12

AIN 12

LBEN

LBEN

A07570

NO.1

. OB9 (MSB)

I

I

lOBO (LSB) I

I

BUSY 1

--,

I

I/O

DATA

BUSS.

I

OB9 (MSB)

.

I

I

A07570

NO. 12

lOBO (LSB) I

I

BUSY 3

NOTE: BSEN ON EACH A07570 IS "ENABLEO" (LOGIC 1).

t

CLK

STRn CD-11

REA01

~ BUSY 1

,OB9,OB8,OB7,OB6,OB5,084,OB3,OB2,081,OBO,

CONVERSION IN PROCESS

L-

READ1

~

~ CD

STRn

BUSY2

REA02

~

CD

STRT 12

BUSY 12

CONVERSION IN PROCESS

CONVERSION IN PROCESS

---1L

READ 2

~

n

READ 12

~

NOTE: STRT SIGNAL 0.5!,s PULSE WIDTH, LEADING

EDGE SYNCHRONIZED TO CLK TRAILING EDGE.

8

Figure 14. Busing Multiple AD7570's

-10-

Figure 15. Timing Diagram

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