AD7570 데이터 시트보기 (PDF) - Analog Devices
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AD7570 Datasheet PDF : 12 Pages
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PIN FUNCTION DESCRIPTION
8
INPUT CONTROLS
8. Vcc (pin 22)
Vcc is the logic power supply. If +5V is used, all control
inputs/outputs (with the exception of comparator terminal)
1. Convert Start (pin 25 - STRT)
When the start inpu t goes to Logical" 1 ", the MS B data
are DTL/TTL compatible. If +15V is applied, control
inputs/outputs are CMOS compatible.
latch is set to Logic "1" and all other data latches are set to
Logic "0". When the start input returns low, the conversion
OUTPUT FUNCTIONS
sequence begins. The start command must remain high for
at least 500 nanoseconds. If a start command is reinitiated
1. Busy (pin 28 - BUSY)
during conversion, the conversion sequence starts over.
The Busy line indicates whether conversion is complete or
2. High Byte Enable (pin 20 - HBEN)
This is a three-state enable for the bit 9 (MSB) and bit 8.
in process. Busy is a three-state output and floats until the
Busy-Enable line is addressed with a Logic "1 ". When
When the control is low, the output data lines for bits
9 and 8 are floating. When the control is high, digital
addressed, Busy will indicate either a "1" (conversion com-
plete) or a "0" (conversion in process).
~
data from the latches appears on the data lines.
3. Low Byte Enable (pin 21 - LBEN)
Same as High Byte Enable pin, but controls bits 0 (LSB)
through 7.
8 4. Busy Enable (pin 27 - BSEN)
This is an interrogation input which requests the status of
Othe converter, i.e., conversion in process or convert com-
plete. The converter status is addressed by applying a Logic
B"1" to the Busy Enable. (See Busy under Output Functions.)
S 5. Short Cycle 8 Bits (pin 26 - SCS)
With a Logic "0" input, the conversion stops after 8 bits
O reducing the conversion time by 2 clock periods. This
<8 L control should be exercised for proper operation of the "J"
version. When a Logic "1" is applied, a complete 10-bit con-
E version takes place ("L" version).
TE 6. Clock (pin 24 - CLK)
2. Serial Output (pin 8 - SRO)
Provides output data in serial format. Data is available only
during conversion. When the A/D is not converting, the
Serial Output line "floats." The Serial Sync (see next func-
tion) must be used, along with the Serial Output terminal
to avoid misinterpreting data.
3. Serial Synchronization (pin 9 - SYNC)
Provides 10 positive edges, which are synchronized to the
Serial Output pin. Serial Sync is floating if conversion is
not taking place.
Note that all digital inputs/outputs are TTL/DTL compatible
when Vcc is +5V, and CMOS compatible when VCC is +15V.
PIN
NO. MNEMONIC
FUNCTION
With an external RC connected, as shown in the figure
below, clock activity begins upon receipt of a Convert-Start
1
VDD
Positive Supply (+ 15V)
command to the A/D and ceases upon completion of con-
version. An external clock (CMOS or TTL/DTL levels) can
directly drive the clock terminals, if required. Figure 2
shows the internal CLK frequency versus Rand C. If Vcc
2
VREF
3
AIN
4
oun
5
OUT2
6
AGND
Voltage REFerence (:t10V)
Analog INput
DAC Current OUTput 1
DAC Current OUTput 2
Analog GrouND
8 ~
is <4.75V, the internal CLK will not operate.
7
COMP
8
SRO
COMParator
SeRial Output
9
SYNC
Serial SYNChronization
10
DB9
Data Bit 9 (MSB)
+5V
(
11
DB8
12
DB7
13
DB6
Data Bit 8
Data Bit 7
Data Bit 6
R
AD7570
24
14
DB5
15
DB4
16
DB3
17
DB2
18
DB1
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
8 ~
CI
Generating Internal Clock Frequency
7. VDD (pin 1)
VDD is the positive supply for all analog circuitry plus some
19
DBO
20
HBEN
21
LBEN
22
VCC
23
DGND
24
CLK
25
STRT
26
SC8
27
BSEN
28
BUSY
Data Bit 0 (LSB)
High Byte ENable
Low Byte ENable
Logic Supply (+ 5V to + 15V)
Digital GrouND
CLocK
STaRT
Short Cycle 8 Bits
BuSy ENable
BUSY
digital logic circuits that are not part of the TTL compatible
input/output lines (back-gates to the P-channel devices).
Nominal supply voltage is +15V.
Table 1. Function Table
-5-
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