AD7570 데이터 시트보기 (PDF) - Analog Devices
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AD7570 Datasheet PDF : 12 Pages
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DYNAMIC PERFORMANCE
Worst case settling requirements occur when a trial bit causes
~
(8
The upper clock frequency limitation (hence the conversion
the OUTI terminal to charge towards a final value which is
speed limitation) of the AD7570 is due to the output settling
precisely 1/2 LSB beyond zero crossing. When this occurs,
the trial bit must settle and remain within 1/2 LSB of final
characteristics of the current weighting DAC in conjunction
with the propagation delay of the comparator, not to speed
val ue, or an incorrect decision will be made by the comparator.
limitations in the digital logic.
For 10-bit accuracy, the first MSB must settle to within 0.1 %
of final value; the second MSB to within 0.2%. The LSB
DAC EQUIVALENT CIRCUIT
settling requirement is only 50% of the LSB value. Figure 8
The Df A converter section of the AD75 70 is a precision lO-bit
multiplying DAc. The simplified DAC circuit, shown in Figure
7, consists of ten single-pole-double-throw current steering
switches and an "inverted" R-2R current weighting network.
(For a complete description of the DAC, refer to the AD7520
data sheet.)
illustrates the settling time available during a given clock
period. The pulse shown on the OUTI terminal falling mid-
way between to and q is a feed through from internal clock
mechanisms and is due primarily to bonding wire and header
capacitance. Two methods may be used to reduce the OUTI
settling time:
.
.
The output resistance and capacitance at OUTI (and OUT2)
J are code dependent, exhibiting resistive variations from 0.5
"R" to 0.75 uR", and capacitive variations from 40pF to
l20pF.
,O(8 VREF
10k
10k
10k
2Ok
20k
20k
8 BSOL I
I
I
I
I
I
oB9
oB8
oB7
20k
20k
A / ANALOG
GNo
OUT2
oun
AIN
ETE Figure 7. DAC Circuit
1. Load OUTI with a lk resistor. This reduces the time
constant by a factor of 10. Further reduction of the lkD.
load reduces the amount of comparator overdrive, thus in-
creasing the comparator propagation delay, resulting in a
reduction of available settling time (tl - to on Figure 8).
2. Use a zero input impedance comparator. Figure 9 illustrates
a comparator circuit which has an input impedance of
approximately 26D.. Proper circuit layout will provide
lO-bit accuracy for clock frequencies >500kHz.
ClK IN
1
COMPARATOR
INPUT
louni
SETTLING TIME ANALYSIS
Due to the changing COUTI and ROUTl, the time constant
on OUTI falls anywhere between 250 and 900ns, depending
on the instantaneous state of the AD7570 digital output code.
NOTES'
1 "',mUNG" "1 . '01 IS THE TIME REOUIRED FOR THE oun TERMINAL TO
SETTLE WITHIN .1/2LS6 OF THE FINAL VALUE.
2. "'COM'" 11, . 1, I IS THE COMPARATOR SWITCHING TIME
3 "'O'lAY" 11, - 1,IIS AN INTERNAllY GENERATED TIME DELAY EOUAL TO
APPROXIMATEL Y 400 NANOSECONDS.
4 COMPARATOR
OUTPUT IS LATCHES
" AT TIME
Figure 8. Expanded Timing Diagram
-8
+5V
Vcc
R1
1k
0.01%
R2
1k
0.01%
R6
1k
. (8
OUT1
AD7570 I
7.5k
R5
0.05%
100
OUT2 R3U
CaMP \AI
!
-15V
R4
7.5k
0.05%
Figure 9. Current Comparator With Low Input Impedance
-7-
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