AD9816 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD9816

Complete 12-Bit 6 MSPS CCD/CIS Signal Processor

Analog Devices 

AD9816

CIRCUIT DESCRIPTIONS

of the AD9816 can also handle an input signal down to

Analog Input Configuration for CDS and SHA Mode

AVSS – 0.3 V without any saturation recovery issues. Although

CDS Mode Operation

Figure 13 shows the equivalent input circuit for the CDS mode

of operation. The CCD signal is connected to the AD9816’s

analog inputs through a coupling capacitor CIN. The CCD

reference level is clamped during the CDSCLK1 pulse, when

the clamp switch closes and connects the externally-generated

an input level below zero volts will be clipped to the ADC’s full-

scale output code, the input stage can respond quickly enough

to accurately process the next pixel that falls into the linear

input range. Any signals below AVSS – 0.3 V will turn on the

input protection diodes, and recovery from the saturated condi-

tion may take up to several milliseconds.

3 V bias to the analog input. After the clamp switch opens

(CDSCLK1 low), the CCD data level will be level shifted by

the voltage held across CIN, and the SHA will sample the input

signal when the CDSCLK2 pulse goes low (see Figures 1 and 3

Input Capacitor CIN

The recommended value for CIN is 1200 pF. This value has

been selected to provide the best overall performance when

considering three factors: input attenuation, linearity and signal

for CDS mode timing). In this sampling technique, the CDS

droop. The value of CIN may be optimized for a particular ap-

OBSOLETE function is effectively performed across the input capacitor, CIN.

This CDS method has two additional considerations. First, the

CCD signal cannot be dc-coupled into the AD9816, because

the input capacitor is required. Second, the input clamp of the

AD9816 is operating as a pixel clamp, and must be asserted on

every pixel for true CDS operation. If line clamp operation is

desired, CDSCLK1 may be used at the start of each line to set

the proper dc voltage on CIN. Then, during the effective pixels

of each line, CDSCLK1 can be held low while CDSCLK2

samples the data levels of each pixel. Figure 5 shows the timing

for line clamp operation.

CCD SIGNAL

AD9816

RS CIN VING IBIAS

11

CSTRAY

BUFFER

SHA

plication if these three factors are understood.

1. Attenuation (Gain Error)

The input voltage will be attenuated by the interaction of

CIN and CSTRAY. CSTRAY is less than 10 pF, which results in

an attenuation of about 0.8% when CIN is 1200 pF. The gain

error will increase accordingly as the value of CIN is decreased.

2. Linearity

The input capacitance of the AD9816 is shown in Figure 8

as CSTRAY. A small portion of this capacitance is junction

capacitance, which will vary nonlinearly as the input voltage

to the AD9816 changes. When the input voltage is attenu-

ated by the combination of CIN and CSTRAY, there will be a

small nonlinear component caused by the input junction

capacitance. The magnitude of the junction capacitance will

cause a 1 LSB (0.024%) nonlinearity over the 3 V input

range when a 1200 pF CIN is used. This nonlinearity will

increase if a smaller CIN is used.

+5V

1␮F 0.1␮F

1.0k⍀

3V

16

OFFSET

1.5k⍀

CLAMP

SWITCH

3. Droop

The input bias current of the AD9816 is typically 10 nA and

is constant regardless of the AD9816’s input voltage. The

droop of the voltage across CIN can be calculated with the

following equation:

17

18

CDSCLK1 CDSCLK2

Figure 13. CDS Mode Input Circuit (All Channels Identical)

Input Signal Range for CDS Mode

An input dc bias level of 3 V allows a maximum 3 V p-p signal

swing from the CCD. Figure 14 shows a typical full-scale input

waveform to the AD9816, illustrating the allowable input range.

With a reference level of 3 V, the AD9816 can tolerate up to

2 V of reset feedthrough above the reference level. The inputs

dV = iBIAS × (t)

CIN

where t is the time between clamp intervals. Between the

adjacent pixels of a scanned line, this droop will be insignifi-

cant. Between scanned lines, a 1 ms delay will produce a

droop of about 10 mV, which can be easily clamped on the

first pixel of the next line. If the value of CIN is reduced, the

droop will increase accordingly.

5V MAX RESET FEEDTHROUGH

3V REFERENCE LEVEL

(SET BY INPUT CLAMP)

MAX PEAK-PEAK SIGNAL

0V MAX DATA LEVEL

–0.3V MAX SATURATED DATA LEVEL

Figure 14. CCD Input Signal Clamped to 3 V

REV. A

–11–

Share Link: