ADSP-21375KSZ-ENG 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21375KSZ-ENG

SHARC® Processor

Analog Devices 

ADSP-21375

KEY FEATURES – PROCESSOR CORE

At 266 MHz (3.75 ns) core instruction rate, the ADSP-21375

performs 1.596 GFLOPs/533 MMACs

0.5M bit on-chip, SRAM for simultaneous access by the core

processor and DMA

2M bit on-chip, mask-programmable, ROM

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single instruction multiple data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in buses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply

operation, an ALU operation, a dual memory read or

write, and an instruction fetch

Transfers between memory and core at a sustained 4.25G

byte/sec bandwidth at 266 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA controller supports:

24 DMA channels for transfers between ADSP-21375 inter-

nal memory and a variety of peripherals

32-bit DMA transfers at peripheral clock speed, in parallel

with full-speed processor execution

16-Bit wide external port provides glueless connection to

both synchronous (SDRAM) and asynchronous memory

devices

Programmable wait state options: 2 to 31 SDCLK cycles

Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

SDRAM accesses at 133 MHz and asynchronous accesses at

42.25 MHz

4 memory select lines allows multiple external memory

devices

Digital applications interface (DAI) includes four serial ports,

four precision clock generators, an input data port, and a

signal routing unit

Digital peripheral interface (DPI) includes, two timers, one

UART, and two SPI ports, and a two wire interface port

Outputs of PCG's C and D can be driven on to DPI pins

Four dual data line serial ports that operate at up to 33M

bits/s on each data line — each has a clock, frame sync and

two data lines that can be configured as either a receiver or

transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Preliminary Technical Data

Up to 8 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port, configurable as eight channels of serial data

or seven channels of serial data and up to a 20-bit wide

parallel data channel

Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components

2 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line /MS pin

1 Muxed Flag/IRQ /MS pin

ROM Based Security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.2 V core

Available in 208-lead MQFP Package (see Ordering Guide on

Page 42)

Rev. PrB | Page 2 of 42 | December 2005

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