ADSP-BF537 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

ADSP-BF537

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF534/ADSP-BF536/ADSP-BF537

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The capabilities of the UARTs are further extended with sup-

port for the infrared data association (IrDA) serial infrared

physical layer link specification (SIR) protocol.

CONTROLLER AREA NETWORK (CAN)

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer

a CAN controller that is a communication controller imple-

menting the CAN 2.0B (active) protocol. This protocol is an

asynchronous communications protocol used in both industrial

and automotive control systems. The CAN protocol is well-

suited for control applications due to its capability to communi-

cate reliably over a network, since the protocol incorporates

CRC checking message error tracking, and fault node

confinement.

The CAN controller offers the following features:

• 32 mailboxes (eight receive only, eight transmit only, 16

configurable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended

(29-bit) identifier (ID) message formats.

• Support for remote frames.

• Active or passive network support.

• CAN wakeup from hibernation mode (lowest static power

consumption mode).

• Interrupts, including: Tx complete, Rx complete, error,

global.

The electrical characteristics of each network connection are

very demanding so the CAN interface is typically divided into

two parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

CAN module represents only the controller part of the interface.

The controller interface supports connection to 3.3 V high-

speed, fault-tolerant, single-wire transceivers.

TWI CONTROLLER INTERFACE

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors

include a 2-wire interface (TWI) module for providing a simple

exchange method of control data between multiple devices. The

TWI is compatible with the widely used I2C® bus standard. The

TWI module offers the capabilities of simultaneous master and

slave operation, support for both 7-bit addressing and multime-

dia data arbitration. The TWI interface utilizes two pins for

transferring clock (SCL) and data (SDA) and supports the

protocol at speeds up to 400k bits/sec. The TWI interface pins

are compatible with 5 V logic levels.

Additionally, the processor’s TWI module is fully compatible

with serial camera control bus (SCCB) functionality for easier

control of various CMOS camera sensor devices.

10/100 ETHERNET MAC

The ADSP-BF536 and ADSP-BF537 processors offer the capa-

bility to directly connect to a network by way of an embedded

Fast Ethernet Media Access Controller (MAC) that supports

both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)

operation. The 10/100 Ethernet MAC peripheral is fully compli-

ant to the IEEE 802.3-2002 standard, and it provides

programmable features designed to minimize supervision, bus

use, or message processing by the rest of the processor system.

Some standard features are:

• Support of MII and RMII protocols for external PHYs.

• Full duplex and half duplex modes.

• Data framing and encapsulation: generation and detection

of preamble, length padding, and FCS.

• Media access management (in half-duplex operation): col-

lision and contention handling, including control of

retransmission of collision frames and of back-off timing.

• Flow control (in full-duplex operation): generation and

detection of PAUSE frames.

• Station management: generation of MDC/MDIO frames

for read-write access to PHY registers.

• SCLK operating range down to 25 MHz (active and sleep

operating modes).

• Internal loopback from Tx to Rx.

Some advanced features are:

• Buffered crystal output to external PHY for support of a

single crystal system.

• Automatic checksum computation of IP header and IP

payload fields of Rx frames.

• Independent 32-bit descriptor-driven Rx and Tx DMA

channels.

• Frame status delivery to memory via DMA, including

frame completion semaphores, for efficient buffer queue

management in software.

• Tx DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations.

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated Rx or Tx IP packet data in mem-

ory after the 14-byte MAC header.

• Programmable Ethernet event interrupt supports any com-

bination of:

• Any selected Rx or Tx frame status conditions.

• PHY interrupt condition.

• Wakeup frame detected.

• Any selected MAC management counter(s) at

half-full.

• DMA descriptor error.

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value.

Rev. B | Page 11 of 68 | July 2006

Share Link: