ALC202 데이터 시트보기 (PDF) - Unspecified
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ALC202 Datasheet PDF : 29 Pages
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Avance Logic, Inc.
SYNC period
Tsync_period
-
20.8
-
SYNC high pulse width
Tsync_high
-
1.3
-
SYNC low pulse width
Tsync_low
-
19.5
-
Note 1: Worse case duty cycle restricted to 45/55.
6.2.4 Data Output and Input Times:
ALC202
us
us
us
Fig 6.2.4-1 Data Output and Input timing diagram
Parameter
Symbol Min Typ Max Units
Output Valid Delay from rising edge of
tco
-
-
15
ns
BIT_CLK
Note 1 : Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the
device driving the output.
Note 2 : 50pF external load
Parameter
Symbol Min Typ Max Units
Input Setup to falling edge of BIT_CLK tsetup
10
-
-
ns
Input Hold from falling edge of BIT_CLK thold
10
-
-
ns
Note : Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the
device driving the output.
Parameter
Symbol Min Typ Max Units
BIT_CLK combined rise or fall plus flight
-
-
7
ns
time
SDATA combined rise or fall plus flight
-
-
7
ns
time
Note : Combined rise or fall plus flight times are provided for worst case scenario
modeling purpose.
6.2.5 Signal Rise and Fall Times:
Fig 6.2.5-1 Signal Rise and Fall timing diagram
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Preliminary
Rev0.62
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