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ALC202 데이터 시트보기 (PDF) - Unspecified

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ALC202
ETC
Unspecified ETC
ALC202 Datasheet PDF : 29 Pages
First Prev 21 22 23 24 25 26 27 28 29
Avance Logic, Inc.
ALC202
6.2.8 AC-Link IO Pin Capacitance and Loading:
Output Pin
1 Codec 2 Codec
BIT_CLK (must support ³ 2 Codecs) 55pF 62.5pF
SDATA_IN
47.5pF 55pF
3 Codec
75pF
60pF
4 Codec
85pF
62.5pF
6.2.9
SPDIF output:
SPDIF_OUT
Rise time/fall time
Duty cycle
Min
Typ
Max
Unit
0
10
%
45
55
%
Note :
T(h)
T(l)
90%
50%
10%
T(r)
T(f)
Rise time = 100 * T(r)/ (T(l)+ T(h)) %
Fall time = 100 * T(f)/ (T(l)+ T(h)) %
Duty cycle = 100 * T(h)/ (T(l)+ T(h)) %
6.2.10 BIT-CLK and SDATA-IN state when RESET# is active:
When RESET# is active the BIT-CLK and SDATA-IN must be floating by internal pull low 100K
resistors. So the ac-link signals are driven by another AC’97 on CNR board. This requirement is not
mentioned in AC’97 specification rev2.1, please refer CNR (Communication Network Riser)
specification rev1.0 page23~25 to get detail information.
7. Analog Performance Characteristics
Standard test conditions: Tambient=250C, Dvdd=3.3V ±5%,Avdd=5.0V±5%
1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms
10KW/50pF load; Test bench Characterization BW: 10Hz~22KHz
0dB attenuation; tone and 3D disabled
Parameter
Min
Typ
Max
Units
Full scale input voltage
Line inputs (Mixers)
-
1.6
-
Vrms
Line inputs (A/D)
-
1.2
-
Mic input (0 dB)
-
1.6
-
Mic input (20 dB boost)
-
0.16
-
Full scale output voltage
LINE-OUT
-
1.0
1.50
Vrms
HEADPHONE-OUT
-
1.7
-
Vrms
- 26 -
Rev0.62
http://www.realtek.com.tw
Preliminary

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