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AT90S8515 데이터 시트보기 (PDF) - Atmel Corporation

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AT90S8515 Datasheet PDF : 112 Pages
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Power-on Reset
The user can select the start-up time according to typical oscillator start-up. The number
of WDT oscillator cycles used for each time-out is shown in Table 4. The frequency of
the Watchdog Oscillator is voltage-dependent as shown in Typical Characteristicson
page 95.
Table 4. Number of Watchdog Oscillator Cycles
FSTRT
Programmed
Time-out at VCC = 5V
0.28 ms
Unprogrammed
16.0 ms
Number of WDT Cycles
256
16K
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 23, an internal timer clocked from the Watchdog Timer oscillator pre-
vents the MCU from starting until after a certain period after VCC has reached the Power-
on Threshold Voltage (VPOT), regardless of the VCC rise time (see Figure 24). The
FSTRT Fuse bit in the Flash can be programmed to give a shorter start-up time if a
ceramic resonator or any other fast-start oscillator is used to clock the MCU.
If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via
an external pull-up resistor. By holding the pin low for a period after VCC has been
applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing
example of this.
Figure 24. MCU Start-up, RESET Tied to VCC.
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
Figure 25. MCU Start-up, RESET Controlled Externally
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
24 AT90S8515
0841G09/01

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