CDP1802AC/3 데이터 시트보기 (PDF) - Intersil

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CDP1802AC/3

High-Reliability CMOS 8-Bit Microprocessor

Intersil 

CDP1802AC/3

Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)

01234567012345670123456

CLOCK

TPA

TPB

MACHINE

CYCLE

CYCLE n

CYCLE (n + 1)

CYCLE (n + 2)

INSTRUCTION

FETCH (S0)

EXECUTE (S1)

INTERRUPT (S3)

MRD

MWR

INTERRUPT

(NOTE)

(INTERNAL) IE

MEMORY

OUTPUT

MEMORY READ CYCLE

NOTE: USER GENERATED SIGNAL

VALID OUTPUT

MEMORY READ, WRITE

OR NON-MEMORY CYCLE

“DON’T CARE” OR INTERNAL DELAYS

NON-MEMORY CYCLE

HIGH IMPEDANCE STATE

FIGURE 12. INTERRUPT CYCLE TIMING WAVEFORMS

Performance Curves

8

LOAD CAPACITANCE (CL) = 50pF

7

6

5

4

VDD = 5V

3

2

1

025 35 45 55 65 75 85 95 105 115 125

AMBIENT TEMPERATURE (TA) (°C)

FIGURE 13. TYPICAL MAXIMUM CLOCK FREQUENCY AS A

FUNCTION OF TEMPERATURE

8

LOAD CAPACITANCE (CL) = 50pF

7

6

5

TA = +25°C

4

3

TA = +125°C

2

1

02

3

4

5

6

7

8

9 10 11 12

SUPPLY VOLTAGE (VDD) (V)

FIGURE 14. TYPICAL MAXIMUM CLOCK FREQUENCY AS A

FUNCTION OF SUPPLY VOLTAGE

FN1441 Rev 3.00

October 17, 2008

Page 13 of 27

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