CXD1196 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1196

CD-ROM DECODER

Sony Semiconductor 

CXD1196AR

Bit4 DECINT (Decoder Interrupt)

If a SYNC mark is detected or internally inserted during execution of the write only, monitor only and

real time correction modes by the DECODER, the DECINT status is created. When the SYNC mark

detected window is open, however, if the SYNC mark spacing is less than 2352 bytes, the DECINT

status is not created. During execution of the repeat correction mode by the DECODER, the

DECINT status is created each time a correction ends.

Bit3 CIERR (Coding Information Error)

When AUTOCI bit of DECCTL register is set at “H” and ADPCM decode playback is done, if there is

an error in a CI byte of an ADPCM sector, the CIERR status is created. ADPCM decode playback of

this sector will not be done.

Bit2-0 RESERVED

2.1.6 Clear Interrupt Status (INCTCLR) Register

When the individual bit of this register is set at ‘H’, the corresponding interrupt status is cleared. The

individual bit is automatically set at ‘L’ after the interrupt status has been cleared. Therefore, there is no

need for the CPU to change the setting at ‘L’.

Bit7 ADPEND (ADPCM End)

Bit6 DECTOUT (DECODER Time Out)

Bit5 DMACMP (DMA Complete)

Bit4 DECINT (DECODER Interrupt)

Bit3 CIERR (Coding Information Error)

Bit2-0 RESERVED

2.1.7 Coding Information (CI) Register

When ADPCM decoding is to be done by setting AUTOCI = ‘L’, the coding information is written to this

register. The bit configuration is the same as that of the coding information byte of the sub header.

2.1.8 DMA Address Counter-L (DMAADRC-L)

2.1.9 DMA Address Counter-H (DMAADRC-H)

This counter retains the address to be used by the CPU when reading data from the buffer. When the data

to be sent to the CPU is read from the buffer, the contents of the DMAADRC are output from MA0-14.

Each time data to be sent to the CPU is read from the buffer, the DMAADRC is incremented.

The CPU sets the head address of DMA in the DMAADRC before starting DMA. The CPU can read and

set the contents of the DMAADRC at any time. Do not change the contents of the DMAADRC during

execution of DMA.

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