CY7C1340G 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1340G Datasheet PDF : 16 Pages
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Pin Configurations
100-Pin TQFP Pinout
CY7C1340G
BYTE C
BYTE D
NC
1
DQc
2
DQc
3
VDDQ
4
VSSQ
5
DQc
6
DQc
7
DQc
8
DQc
9
VSSQ
10
VDDQ
11
DQc
12
DQc
13
NC
14
VDD
NC
15
16
VSS
17
DQD
18
DQD
19
VDDQ
VSSQ
20
21
DQD
22
DQD
23
DQD
24
VDSQSQD
25
26
VDDQ
27
DQD
28
DQD
29
NC
30
CY7C1340G
80
NC
79
DQB
78
DQB
77
VDDQ
76
VSSQ
75
DQB
74
DQB
73
DQB
72
DQB
71
VSSQ
70
VDDQ
69
DQB
68
67
DQB
VSS
66
NC
65
64
VDD
ZZ
63
62
61
DQA
DQA
VDDQ
60
VSSQ
59
DQA
58
DQA
57
DQA
56
DQA
55
VSSQ
54
VDDQ
53
DQA
52
DQA
51
NC
BYTE B
BYTE A
Pin Definitions
Pin
A0, A1, A
BWA, BWB,
BWC, BWD
GW
BWE
Type
Description
Input- Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] are
fed to the two-bit counter.
Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Document #: 38-05522 Rev. *D
Page 3 of 16
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