CY7C1340G 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1340G Datasheet PDF : 16 Pages
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CY7C1340G
Pin Definitions (continued)
Pin
Type
Description
CLK
Input- Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
Clock counter when ADV is asserted LOW, during a burst operation.
CE1
Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded.
OE
Input- Output Enable, asynchronous input, active LOW. Controls the direction of the DQ pins. When
Asynchronous LOW, the DQ pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
ADV
Input- Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
ADSC
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE1 is deasserted HIGH.
Input- Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized.
ZZ
Input- ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved.During normal operation, this pin has to be low or left
floating. ZZ pin has an internal pull-down.
DQs
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
are placed in a tri-state condition.
VDD
VSS
VDDQ
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O Power Power supply for the I/O circuitry.
Supply
VSSQ
MODE
I/O Ground
Input-
Static
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC,NC/9M,
NC/18M,
NC/36M,
NC/72M
No Connects. Not internally connected to the die.NC/9M,NC/18M,NC/36M,NC/72M are address
expansion pins are not internally connected to the die.
Document #: 38-05522 Rev. *D
Page 4 of 16
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