H5PS1G43EFR 데이터 시트보기 (PDF) - Hynix Semiconductor
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H5PS1G43EFR Datasheet PDF : 44 Pages
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H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
Timing Patterns for 8 bank devices x16
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D
-DDR2-667 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
DDD
-DDR2-800 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
DDDD
3.5. Input/Output Capacitance
Parameter
Symbol
DDR2 400
DDR2 533
Min Max
Input capacitance, CK and CK
CCK
1.0
2.0
Input capacitance delta, CK and CK
CDCK
x
0.25
Input capacitance, all other input-only pins
CI
1.0
2.0
Input capacitance delta, all other input-only pins
CDI
x
0.25
Input/output capacitance, DQ, DM, DQS, DQS
CIO
2.5
4.0
Input/output capacitance delta, DQ, DM, DQS, DQS CDIO
x
0.5
DDR2 667
Min Max
1.0
2.0
x
0.25
1.0
2.0
x
0.25
2.5
3.5
x
0.5
DDR2 800
Min Max
Units
1.0
2.0
pF
x
0.25
pF
1.0 1.75
pF
x
0.25
pF
2.5
3.5
pF
x
0.5
pF
Rev. 0.4 / Nov 2008
20
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