HI5702 데이터 시트보기 (PDF) - Intersil

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HI5702

10-Bit, 40 MSPS A/D Converter

Intersil 

HI5702

Signal-to-Noise Ratio (SNR)

Full Power Input Bandwidth (FPBW)

SNR is the measured RMS signal to RMS noise at a speci-

fied input and sampling frequency. The noise is the RMS

sum of all of the spectral components except the fundamen-

tal and the first five harmonics.

Signal-to-Noise + Distortion Ratio (SINAD)

SINAD is the measured RMS signal to RMS sum of all

other spectral components below the Nyquist frequency

excluding DC.

Effective Number of Bits (ENOB)

The effective number of bits (ENOB) is calculated from the

SINAD data by

ENOB = (SINAD - 1.76 + VCORR) / 6.02

where: VCORR = 0.5dB

VCORR adjusts the ENOB for the amount the input is below

fullscale.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the fundamental input signal.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the applicable harmonic

component to the RMS value of the fundamental input signal.

Intermodulation Distortion (IMD)

Nonlinearities in the signal path will tend to generate

intermodulation products when two tones, f1 and f2, are

present on the inputs. The ratio of the measured signal to

the distortion terms is calculated. The terms included in the

calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2),

(2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each

tone 6dB below full scale.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spur or spectral compo-

nent in the spectrum below fS/2.

Transient Response

Transient response is measured by providing a full scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

10-bit accuracy.

Overvoltage Recovery

Overvoltage Recovery is measured by providing a full scale

transition to the analog input of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 10-bit accuracy.

Full power bandwidth is the frequency at which the ampli-

tude of the digitally reconstructed output has decreased 3dB

below the amplitude of the input sine wave. The input sine

wave has a peak-to-peak amplitude equal to the reference

voltage. The bandwidth given is measured at the specified

sampling frequency.

Video Definitions

Differential gain and Differential Phase are two commonly

found video specifications for characterizing the distortion of

a chrominance (3.58MHz) signal as it is offset through the

input voltage range of an ADC.

Differential Gain (DG)

Differential Gain is the peak difference in chrominance

amplitude (in percent) at two different DC levels.

Differential Phase (DP)

Differential Phase is the peak difference in chrominance

phase (in degrees) at two different DC levels.

Timing Definitions

Refer to Figure 1 and Figure 2 for these definitions.

Aperture Delay (tAD)

Aperture delay is the time delay between the external sam-

ple command (the falling edge of the clock) and the time at

which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Aperture Jitter (tAJ)

This is the RMS variation in the aperture delay due to varia-

tion of internal clock path delays.

Data Hold Time (tH)

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

Data Output Delay Time (tOD)

Data output delay time is the time to where the new data (N)

is valid.

Data Latency (tLAT)

After the analog sample is taken, the data on the bus is out-

put at 7th cycle of the clock. This is due to the pipeline

nature of the converter where the data has to ripple through

the stages. This delay is specified as the data latency. After

the data latency time, the data representing each succeed-

ing sample is output at the following clock pulse. The digital

data lags the analog input by 7 cycles.

Power-Up Initialization

This time is defined as the maximum number of clock cycles

that are required to initialize the converter at power-up. The

requirement arises from the need to initialize the dynamic

circuits within the converter.

4-1515

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