HM6264BI 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HM6264BI

64k SRAM (8-kword × 8-bit) Wide Temperature Range version

Hitachi -> Renesas Electronics 

HM6264BI Series

AC Characteristics (Ta = –40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.)

Test Conditions

• Input pulse levels: 0.6 V to 2.4 V

• Input and output timing reference level: 1.5 V

• Input rise and fall time: 10 ns

• Output load: 1 TTL Gate + CL (100 pF) (Including scope & jig)

Read Cycle

HM6264BI-10 HM6264BI-12

Parameter

Symbol Min Max Min Max Unit Notes

Read cycle time

t RC

100 — 120 — ns

Address access time

t AA

—

100 —

120 ns

Chip select access time

CS1 tCO1

—

100 —

120 ns

CS2 tCO2

—

100 —

120 ns

Output enable to output valid

t OE

—

50 —

60 ns

Chip selection to output in low-Z

CS1 tLZ1

10

—

10

—

ns

2

CS2 tLZ2

10

—

10

—

ns

2

Output enable to output in low-Z

t OLZ

5

—5

—

ns

2

Chip deselection in to output in high-Z CS1 tHZ1

0

35 0

40

ns

1, 2

CS2 tHZ2

0

35 0

40

ns

1, 2

Output disable to output in high-Z

t OHZ

0

35 0

40

ns

1, 2

Output hold from address change

t OH

10 — 10 — ns

Notes: 1. tHZ is defined as the time at which the outputs achieve the open circuit conditions and are not

referred to output voltage levels.

2. At any given temperature and voltage condition, tHZ maximum is less than tLZ minimum both for a

given device and from device to device.

3. Address must be valid prior to or simultaneously with CS1 going low or CS2 going high.

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