ICL7112 데이터 시트보기 (PDF) - Intersil

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ICL7112

12-Bit, High-Speed, CMOS µP-Compatible A/D Converter

Intersil 

ICL7112

VIN +

SOURCE -

VREF -

SOURCE +

VIN

ICL7112

VREF

AGND

DGND

FIGURE 4. RECOMMENDED GROUNDING TECHNIQUE TO ELIMINATE GROUND LOOP ERRORS

ADDRESS BUS

A0

A0

ICL7112

CS

RD

WR

BUS

OVR

D0 - D7 D8 - D11

ADDRESS

DECODE

A0 - AN

CS

RD

WR

µP

OVR

D0 - D7

DATA BUS

WR

CS

A0

RD

START

CONVERSION

WAIT

READ

LOW BYTE

READ

HIGH BYTE

FIGURE 5. “START AND WAIT” OPERATION

By adding a three-state buffer and two control gates, the

End-of-Conversion (EOC) output can be used to control a

“Start and Poll” interface (Figure 6). In this mode, the A0 and

CS lines connect the EOC output to the data bus along with

the most significant byte of data. After pulsing the WR line to

initiate a conversion, the microprocessor continually reads

the most significant byte until it detects a high level on the

EOC bit. The “Start and Poll” interface increases data

throughput compared with the “Start and Wait” method by

eliminating delays between the conversion termination and

the microprocessor read operation.

Other interface configurations can be used to increase data

throughput without monopolizing the microprocessor during

waiting or polling operations by using the EOC line as an

interrupt generator as shown in Figure 7. After the conver-

sion cycle is initiated, the microprocessor can continue to

execute routines that are independent of the A/D converter

until the converter’s output register actually holds valid data.

For fastest data throughput, the ICL7112 can be connected

directly to the data bus but controlled by way of a Direct

6-8

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