IDT72V71660 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72V71660
Integrated Device Technology
IDT72V71660 Datasheet PDF : 31 Pages
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IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURE RANGE
DELAY THROUGH THE IDT72V71660
The switching of information from the input serial streams to the output serial
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on a per-channel basis. For voice applications, variable throughput delay
is best as it ensure minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
The delay through the device varies according to the type of throughput delay
selected in the Switching Mode Selection bits of the Connection Memory.
VARIABLE DELAY MODE (MOD1-0 = 0-0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V71660 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if the
input channel n is switched to output channel n+1 or n+2. If the input channel
n is switched to output channel n+3, n+4,..., the new output data will appear in
the same frame. Table 2 shows the possible delays for the IDT72V71660 in
Variable Delay mode.
CONSTANT DELAY MODE (MOD1-0 = 0-1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V71660, the minimum throughput delay achievable in Constant Delay
mode will be one frame plus one channel. See Table 1.
MICROPROCESSOR INTERFACE
The data in the Control Register consists of the Memory Block Programming
bit, the Block Programming Data bits, the Begin Block Programming Enable, the
Output Stand By, Start Frame Evaluation, Output Enable Indication and Data
Rate Select bits. As explained in the Memory Block Programming section, the
Block Programming Enable begins the programming if the MBP bit is enabled.
This allows the entire Connection Memory block to be programmed with the
Block Programming Data bits. If the ODE pin is LOW, the Output Stand By bit
enables (if HIGH) or disables (if LOW) all TX output drivers. If the ODE pin is
HIGH, the Output Stand By bit is ignored and all TX output drivers are enabled.
SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As
with the hard reset, the Software Reset must also be set HIGH for 20ns before
bringing the Software Reset LOW again for normal operation. Once the Software
Reset is LOW, internal registers and other memories may be read or written.
During Software Reset, the microprocessor port is still able to read from all
internal memories. The only write operation allowed during a Software Reset
is to the Software Reset bit in the Control Register to complete the Software Reset.
CONNECTION MEMORY CONTROL
If the ODE pin and the Output Stand By bit are LOW, all output channels will
be in three-state. See Table 3 for detail.
If MOD1-0 of the Connection Memory is 1-0 accordingly, the output channel
will be in Processor Mode. In this case the lower eight bits of the Connection
Memory are output each frame until the MOD1-0 bits are changed. If MOD1-
0 of the Connection Memory are 0-1 accordingly, the channel will be in Constant
Delay Mode and bits 13-0 are used to address a location in Data Memory. If
MOD1-0 of the Connection Memory are 0-0, the channel will be in Variable
Delay Mode and bits 13-0 are used to address a location in Data Memory. If
MOD 1-0 of the Connection Memory are 1-1, the channel will be in high
Impedance mode and that channel will be in three-state.
The IDT72V71660’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 16-bit address bus and a
16-bit data bus, reads and writes are mapped directly into Data and Connection
Memories and require only one clock cycle to access. By allowing the internal
memories to be randomly accessed in one cycle, the controlling microprocessor
has more time to manage other peripheral devices and can more easily and
quickly gather information and setup the switch paths. Table 4 shows the
mapping of the addresses into internal memory blocks.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal registers
and memories of the IDT72V71660.
The two most significant bits of the address select between the registers, Data
Memory, and Connection Memory. If A15 and A14 are HIGH, A13-A0 are used
to address the Data Memory. If A15 is HIGH and A14 is LOW, A13-A0 are used
to address Connection Memory. If A15 is LOW and A14 is HIGH A13-A0 are
used to select the Control Register, Frame Alignment Register, and Frame Offset
Registers. See Table 4 for mappings.
As explained in the Serial Data Interface Timing and Switching Configurations
sections, after system power-up, the Control Register should be programmed
immediately to establish the desired switching configuration.
OUTPUT ENABLE INDICATION
The IDT72V71660 has the capability to indicate the state of the outputs (active
or three-state) by enabling the Output Enable Indication in the Control Register.
In the Output Enable Indication mode however, only half of the output streams
are available. If this same capability is desired with all 64 streams, this can be
accomplished by using two IDT72V71660 devices. In one device, the All Output
Enable bit is set to a one while in the other the All Output Enable is set to zero.
In this way, one device acts as the switch and the other as a three-state control
device, see Figure 5. It is important to note if the TSI device is programmed for
All Output Enables and the Output Enable Indication is also set, the device will
be in the All Output Enables mode not Output Enable Indication. To use all 64
streams, set Output Enable Indication in the Control Register to zero.
INITIALIZATION OF THE IDT72V71660
After power up, the state of the Connection Memory is unknown. As such,
the outputs should be put in high-impedance by holding the ODE pin LOW. While
the ODE is LOW, the microprocessor can initialize the device by using the Block
Programming feature and program the active paths via the microprocessor bus.
Once the device is configured, the ODE pin (or Output Stand By bit depending
on initialization) can be switched to enable the TSI switch.
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