IDT72V71660 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72V71660
Integrated Device Technology
IDT72V71660 Datasheet PDF : 31 Pages
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IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURE RANGE
TABLE 1 — CONSTANT THROUGHPUT
DELAY VALUE
Input Rate
2.048Mb/s
4.096Mb/s
8.192Mb/s
16.384Mb/s
Delay for Constant Throughput Delay Mode
(m – output channel number)
(n – input channel number)
32 + (32 – n) +m time-slots
64 + (64 – n) +m time-slots
128 + (128 – n) +m time-slots
256 + (256 – n) +m time-slots
TABLE 2 — VARIABLE THROUGHPUT
DELAY VALUE
Input Rate
2.048Mb/s
Delay for Variable Throughput Delay Mode
(m – output channel number; n – input channel number)
m ≤ n+2
m > n+2
32 – (n-m) time-slots
(m-n) time-slots
4.096Mb/s
8.192Mb/s
64 – (n-m) time-slots
128 – (n-m) time-slots
(m-n) time-slots
(m-n) time-slots
16.384Mb/s
256 – (n-m) time-slots
(m-n) time-slots
TABLE 3 — OUTPUT HIGH-IMPEDANCE CONTROL
Bits MOD1-0 Values in
Connection Memory
1 and 1
ODE pin
Don’t Care
OSB bit in Control
Register
Don’t Care
Any, other than 1 and 1
0
0
Any, other than 1 and 1
0
1
Any, other than 1 and 1
1
0
Any, other than 1 and 1
1
1
Output Status
Per-channel
high-Impedance
high-Impedance
Enable
Enable
Enable
TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R/W
Location
1 1 STA5 STA4 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R
Data Memory
1 0 STA5 STA4 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R/W Connection Memory
0 1 0 0 0 0 0 x x x x x x x x x R/W
Control Register
0 1 0 0 0 0 1 x x x x x x x x x R FrameAlignRegister
0 1 1 0 0 0 0 x x x x x x x x x R/W Frame Offset Register 0
0 1 1 0 0 0 1 x x x x x x x x x R/W Frame Offset Register 1
0 1 1 0 0 1 0 x x x x x x x x x R/W Frame Offset Register 2
0 1 1 0 0 1 1 x x x x x x x x x R/W Frame Offset Register 3
0 1 1 0 1 0 0 x x x x x x x x x R/W Frame Offset Register 4
0 1 1 0 1 0 1 x x x x x x x x x R/W Frame Offset Register 5
0 1 1 0 1 1 0 x x x x x x x x x R/W Frame Offset Register 6
0 1 1 0 1 1 1 x x x x x x x x x R/W Frame Offset Register 7
0 1 1 1 0 0 0 x x x x x x x x x R/W Frame Offset Register 8
0 1 1 1 0 0 1 x x x x x x x x x R/W Frame Offset Register 9
0 1 1 1 0 1 0 x x x x x x x x x R/W Frame Offset Register 10
0 1 1 1 0 1 1 x x x x x x x x x R/W Frame Offset Register 11
0 1 1 1 1 0 0 x x x x x x x x x R/W Frame Offset Register 12
0 1 1 1 1 0 1 x x x x x x x x x R/W Frame Offset Register 13
0 1 1 1 1 1 0 x x x x x x x x x R/W Frame Offset Register 14
0 1 1 1 1 1 1 x x x x x x x x x R/W Frame Offset Register 15
NOTE: Unused STA and CH bits should be set to zero.
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