IDT72V71660 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72V71660
Integrated Device Technology
IDT72V71660 Datasheet PDF : 31 Pages
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IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
TABLE 5 — CONTROL REGISTER (CR) BITS
Reset Value:
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
SRS OEI OEPOL AOE
0
0 MBP BPD1 BPD0 BPE OSB SFE
INDUSTRIAL TEMPERATURE RANGE
3
2
1
0
0
0
DR1 DR0
BIT NAME
DESCRIPTION
15
SRS
(Software Reset)
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
14
OEI
When 1, the TX32-63/OEI0-31 pins will be OEI0-31 and reflect the active or high-impedance state of their corresponding output data
(OutputEnableIndication) streams. When 0, this feature is disabled and these pins are used as output data streams TX32-63.
13
OEPOL
When 1, a one on an Output Enable Indication pin denotes an active state on the output data stream; zero on an Output Enable Indication
(OutputEnablePolarity) pindenoteshigh-impedancestate. When0,aoneonanOutputEnableIndicationpindenoteshigh-impedanceandazerodenotes
an active state.
12
AOE
(All Output Enables)
When 1, TX0-63 will behave as OEI0-63 accordingly. These outputs will reflect the active or high-impedance state of the
corresponding output data streams (TX0-63) in another IDT72V71660 if programmed identically. When 0, the TSI operates in the normal
switch mode.
11-10 Unused
Must be zero for normal operation.
9
MBP
When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits,
(Memory Block Program) bit 14 and bit 15. When 0, this feature is disabled.
8-7
BPD1-0
(Block Programming
Data)
These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature
is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to 1,
the contents of the bits Block Programming Data1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of the
Connection Memory are set to 0.
6
BPE
A zero to one transition of this bit enables the memory block programming function. Once the Block Programming Enable
(Begin Block
bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished,
Programming Enable)
the Block Programming Enable, Memory Block Program and Block Programming Data1-0 bits will be reset to zero by the device
to indicate the operation is complete.
5
OSB
(Output Stand By)
When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When
either ODE = 1 or Output Stand By =1 the output serial streams drivers function normally.
4
SFE
A zero to one transition in this bit starts the Frame Evaluation procedure. When the Complete Frame Evaluation bit in the Frame Alignment
(Start Frame Evaluation) Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this bit to zero for
at least one frame.
3-2
Unused
Must be zero for normal operation.
1-0
DR1-0
DR1
(Data Rate Select)
0
0
1
1
DR0
Data Rate
Master Clock
0
2.048Mb/s
4.096 MHz
1
4.096Mb/s
8.192 MHz
0
8.192Mb/s
16.384 MHz
1
16.384Mb/s
16.384 MHz
8
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