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IS24C128A

128K-bit/ 256K-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution 

IS24C128A

IS24C256A

Page Write

The IS24C128A/256A is capable of 64-byte Page-Write

operation. A Page-Write is initiated in the same manner as a

Byte Write, but instead of terminating the internal Write cycle

after the first data word is transferred, the Master device can

transmit up to 63 more bytes. After the receipt of each data

word, the IS24C128A/256A responds immediately with an

ACK on SDA line, and the six lower order data word address

bits are internally incremented by one, while the higher order

bits of the data word address remain constant. If a byte

address is incremented from the last byte of a page, it

returns to the first byte of that page. If the Master device

should transmit more than 64 words prior to issuing the Stop

condition, the address counter will “roll over,” and the previously

written data will be overwritten. Once all 64 bytes are

received and the Stop condition has been sent by the Master,

the internal programming cycle begins. At this point, all

received data is written to the IS24C128A/256A in a single

Write cycle. All inputs are disabled until completion of the

internal Write cycle.

Acknowledge (ACK) Polling

The disabling of the inputs can be used to take advantage

of the typical Write cycle time. Once the Stop condition

is issued to indicate the end of the host's Write operation,

the IS24C128A/256A initiates the internal Write cycle. ACK

polling can be initiated immediately. This involves issuing

the Start condition followed by the Slave address for a

Write operation. If the IS24C128A/256A is still busy with the

Write operation, no ACK will be returned. If the IS24C128A/

256A has completed the Write operation, an ACK will be

returned and the host can then proceed with the next Read

or Write operation.

READ OPERATION

Read operations are initiated in the same manner as Write

operations, except that the (R/W) bit of the Slave address

is set to “1”. There are three Read operation options:

current address read, random address read, and sequential

read.

Current Address Read

The IS24C128A/256A contains an internal address counter

which maintains the address of the last byte accessed,

incremented by one. For example, if the previous operation

is either a Read or Write operation addressed to the

address location n, the internal address counter would

increment to address location n+1. When the IS24C128A/

256A receives the Slave Device Addressing Byte with a

Read operation (R/W bit set to “1”), it will respond an ACK

and transmit the 8-bit data word stored at address location

n+1. The Master should not acknowledge the transfer but

ISSI ®

should generate a Stop condition so the IS24C128A/256A

discontinues transmission. If 'n' is the last byte of the

memory, the data from location '0' will be transmitted. (Refer

to Figure 8. Current Address Read Diagram.)

Random Address Read

Selective Read operations allow the Master device to select

at random any memory location for a Read operation. The

Master device first performs a 'dummy' Write operation by

sending the Start condition, Slave address and word address

of the location it wishes to read. After the IS24C128A/256A

acknowledges the word address, the Master device resends

the Start condition and the Slave address, this time with the

R/W bit set to one. The IS24C128A/256A then responds

with its ACK and sends the data requested. The Master

device does not send an ACK but will generate a Stop

condition. (Refer to Figure 9. Random Address Read

Diagram.)

Sequential Read

Sequential Reads can be initiated as either a Current

Address Read or Random Address Read. After the

IS24C128A/256A sends the initial byte sequence, the

Master device now responds with an ACK indicating it

requires additional data from the IS24C128A/256A. The

IS24C128A/256A continues to output data for each ACK

received. The Master device terminates the sequential

Read operation by pulling SDA High (no ACK) indicating the

last data word to be read, followed by a Stop condition.

The data output is sequential, with the data from address n

followed by the data from address n+1, ... etc. The address

counter increments by one automatically, allowing the

entire memory contents to be serially read during sequential

Read operation. When the memory address boundary of

16383 or 32767 (depending on the device) is reached, the

address counter “rolls over” to address 0, and the IS24C128A/

256A continues to output data for each ACK received.

(Refer to Figure 10. Sequential Read Operation Starting with

a Random Address Read Diagram.)

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

5

ADVANCEDINFORMATION Rev. 00B

06/27/06

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