LX64EV-5F100I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LX64EV-5F100I

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

Figure 7. I/O Pin Connection to the sysCLOCK PLL1

PLL_LOCK

CLK_OUT

GCLK_IN

Input Clock

(M) Divider

÷ 1 to 32

Programmable

+ Delay

--------------------

Programmable

- Delay

PLL (n)

Post-scalar

(V) Divider

÷

1, 2, 4, 8,

16, 32

Clock

(K) Divider

÷

2, 4, 8,

16, 32

Feedback

Divider (N)

x 1 to 32

Clock Net

To Adjacent_PLL

From Adjacent_PLL

PLL_FBK

GRP

PLL_RST

ispGDX2 Family Data Sheet

Output

Reg/

Latch

Input

Reg/

Latch

Delay

GDX Block

GCLK_IN

1. Some pins are shared. See Logic Signal Connections Table for details.

Resetb (0)

Control Array

(from selected blocks)

11

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