K8A55EBC 데이터 시트보기 (PDF) - Samsung
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K8A55EBC Datasheet PDF : 64 Pages
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K8A56(57)15ET(B)(Z)C
Rev. 1.0
datasheet NOR FLASH MEMORY
7.0 PRODUCT INTRODUCTION
The K8A(56/57)15E is 256Mbit (268,435,456 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within
the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs.
The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device
adapts a block memory architecture that divides its memory array into 256 blocks (64-Kword x 256 blocks, Uniform block part) / 259 blocks (16-Kword x 4
+ 64-Kword x 255, Boot block part). Programming is done in units of 16 bits (Word). Programming is done in units of 16 bits (Word). All bits of data in one
or multiple blocks can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the pro-
grammed data, 256 / 259 memory blocks can be hardware protected. Regarding read access time, the K8A5615E provides 11ns burst access time and
95ns initial access time at 66MHz. At the K8A5615E provides 9ns burst access time and 95ns initial access time at 83MHz. At the K8A5715E provides
7ns burst access time and 95ns initial access time at 108MHz. At 133MHz, the K8A5715E provides 6ns burst access time and 95ns initial access time.
The command set of K8A(56/57)15E is compatible with standard Flash devices. The device uses Chip Enable (CE), Write Enable (WE), Output Enable
(OE) to control asynchronous read and write operation. For burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device oper-
ations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command
registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry.
Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8A(56/57)15E is implemented
with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines are invoked by program/erase
command sequences. The Internal Program Routine automatically programs and verifies data at specified addresses. The Internal Erase Routine auto-
matically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8A(56/57)15E has means to indicate the
status of completion of program/erase operations. The status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have
been completed, the device automatically resets itself to the read mode. The device requires only 35mA as burst and asynchronous mode read current
and 25 mA for program/erase operations.
[Table 7] Device Bus Operations
Operation
Asynchronous Read Operation
Write
Standby
Hardware Reset
Load Initial Burst Address
Burst Read Operation
Terminate Burst Read Cycle
Terminate Burst Read Cycle via RESET
Terminate Current Burst Read Cycle and Start
New Burst Read Cycle
NOTE : L=VIL (Low), H=VIH (High), X=Don’t Care.
CE
OE
WE
A0-23
L
L
H
Add In
DQ0-15
I/O
RESET
H
CLK
L
AVD
L
L
H
Add In
I/O
H
L
X
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
X
H
L
L
H
X
Burst
DOUT
H
H
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
I/O
H
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