SAA7206 데이터 시트보기 (PDF) - Philips Electronics

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SAA7206

DVB compliant descrambler

Philips Electronics 

Philips Semiconductors

DVB compliant descrambler

Product specification

SAA7206H

7.4 Microcontroller interface

The microcontroller interface provides a means of

communication between a system controller (for instance

“Philips 90CE201”) in a digital TV receiver and the

descrambler internal registers and buffers. The physical

interface consists of:

• DAT7 to DAT0; an 8-bit wide bidirectional data bus.

Data and address information are multiplexed on this

bus.

• DCS; an active LOW chip select signal.

The descrambler only responds to microcontroller

communication if this signal is driven LOW.

• R/W; an active HIGH read signal, indicating that the

microcontroller is attempting to read data from registers

or buffers inside the descrambler. If this signal is LOW,

data is being written to registers or buffers inside the

descrambler.

• A1 and A0; a 2-bit address bus. If the least significant

address bit (0) is logic 0, the most significant byte of a

16-bit register is addressed, otherwise the least

significant byte is selected. If the most significant

address bit (1) is logic 1 DAT7 to DAT0 carries the

address information, otherwise it will carry control data.

• IRQ; an active LOW (open-drain output) interrupt

request signal. An interrupt is set if one of the15 bits in

the descramblers internal interrupt register is set.

The interrupt mechanism consists of three 15-bit

registers and one 4-bit register, as illustrated in Fig.8.

The interrupt status register enables the microcontroller

to monitor the momentary status of the interrupts.

This is particularly useful during read operations in the

descramblers CA buffers, as the interrupt status bits in

question [‘flt0_stat’, ‘flt1_stat’, etc. (see Table 10,

addresses 0x0002 and 0x0004)] are reset when the

buffers have been emptied or released.

The interrupt mask register (see Table 10,

address 0x0001) prevents individual interrupts from

resetting IRQ (to logic 0). The interrupt status bits are

logically ANDed with the mask. If a rising edge occurs on

one of the resulting signals, it is latched into the interrupt

register, thus resetting IRQ.

handbook, half0paxg0e002/0x0004

(read only)

19-bit status

0x0001

(write only)

15-bit mask

0x0000

(read/write)

15-bit interrupt

momentary status of the

individual interrupt bits

enables/disables

individual interrupts

latched interrupts, indicating

which interrupt(s) set IRQ

IRQ

MGG320

The interrupt register is reset when addressed.

Fig.8 Descrambler version 3, microcontroller

interrupt mechanism.

Table 6 Definition of interrupt mechanism; see Fig.8

BIT NUMBER

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

MEANING OF INTERRUPT

filter 0 retrieved CA data

filter 1 retrieved CA data

filter 2 retrieved CA data

filter 3 retrieved CA data

filter 4 retrieved CA data

filter 5 retrieved CA data

filter 6 retrieved CA data

filter 7 retrieved CA data

filter 8 retrieved CA data

filter 9 retrieved CA data

filter 10 retrieved CA data

filter 11 retrieved CA data

filter 12 retrieved CA data

filter 13 retrieved CA data

filter 14, 15, 16 or 17 retrieved

CA data

empty

1996 Oct 09

15

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