SAA7206 데이터 시트보기 (PDF) - Philips Electronics

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SAA7206

DVB compliant descrambler

Philips Electronics 

Philips Semiconductors

DVB compliant descrambler

Product specification

SAA7206H

The interrupt register itself is reset

(to 0000000000000000) as soon as it is addressed

(0x0000) by the microcontroller.

A typical example of communication between

microcontroller and descrambler is illustrated in Fig.9.

The descrambler contains an auto increment address

counter which can be loaded by performing a write

address operation. The present operation, whether read or

write, is now performed on the current address. The next

operation, whether read or write, is performed on the

current address plus 1.

Remark: Avoid resetting the auto increment address

counter to 0x0000, when not handling interrupts, as

addressing it causes the interrupt register to be reset.

Consequently, interrupt information might be lost.

The descrambler internal register and buffer addresses

are organized as illustrated in Fig.10. The first 4 address

bits (15 to 12) are used to select either the descrambler

registers (equals 0) or one of the descrambler buffers

(ranges 1 and 2).

In the buffer mode, the remaining address bits (11 to 0) are

part of the word address (range depending on the buffer,

see Table 10). In the register mode, bits 11 to 8 specify

the register unit number (see Fig.10). The remaining 8 bits

of the address (7 to 0) indicate specific register addresses

within a selected unit. The address range in a specific

register unit depends on the number of registers present

and is different for each unit. For details refer to Table 10.

The CA filter module in the microcontroller interface unit is

capable of accessing general CA messages (ECM and

EMM, etc.) in the transport stream. The CA filter module

consists of 18 filters and 18 buffers of 256 bytes each,

thus each filter has its own data buffer. The 18 filters are

divided into two types of filters, which are specified in

Table 9. For each filter the ‘table_id’ of the section (the first

byte of the section see Fig.9), can be masked.

The architecture of the 9 CA filter pairs is shown in Fig.11.

handbook, full pAag1ewidth

A0

R/W

DCS

DAT7 to

DAT0

>24 ns

MSByte

LSByte

>666 ns

write address N

MSByte

LSByte

>666 ns

read data @ N

MSByte

LSByte

write data @ N+1

MGG321

The descrambler internal register address is incremented automatically.

Fig.9 Microcontroller descrambler communication (example).

1996 Oct 09

16

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