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SAA7206

DVB compliant descrambler

Philips Electronics 

Philips Semiconductors

DVB compliant descrambler

Product specification

SAA7206H

If the microcontroller decides to read data from one of the

CA buffers (see Table 10, address range filter_0:

0x2000 to 0x207F to filter_17: 0x2880 to 0x28FF) it can

determine when to stop reading in two ways. It can

periodically poll the ‘flt0_stat’ to ‘flt17_stat’ bits in the

interrupt status register (see Table 10, address 0x0002

and 0x0004). Each of these bits goes LOW as soon as the

last valid section data is read from the associated CA

buffer.

Another possibility is to read the ‘high_flt_address’ word

(‘haddr7 to 0’, Table 10, addresses 0x0302 to 0x0313).

The high address indicates the number of valid section

words (1 word = 2 bytes) that were written into the buffer.

This number equals the number of read cycles that has to

be performed to retrieve all valid data from the buffer.

If the buffer contents have to be removed without being

read, the microcontroller can write a logic 1 to the

‘rst_bf17-0’ bit (see Table 10, address 0x0314 and

0x0315) thus releasing the buffer. Another possibility is to

perform a write address operation with a value of

haddr7 to haddr0 plus buffer base address. The internal

auto increment address counter is thus set to the last word

in the buffer, causing the interrupt status bit to be reset and

the filters to be reactivated, after having been idle during

buffer emptying.

If, during the acquisition of a CA message, one of the TS

packets composing a message contains an error

(‘transport_error_indicator’ = ‘1’) the erroneous TS packet

is removed and CA message acquisition is restarted. Thus

the complete CA message is lost when at least one of the

TS packets which composes this message contains an

error. Duplicate TS packets containing CA messages are

also removed.

7.5 Output interfacing

The output data stream consists of a sequence of bytes.

A new byte is present at the data output pins

DATO7 to DATO0 at each rising edge of the descrambler

chip clock DCLK. The control signals SYNCO and DVO

are a delayed (9 MHz) version of the input interface signals

MSYNC and MDV respectively. By this form of delay

correction the relationship between the data and control

signals is maintained.

The MB/MB and MBCLK signals are not output to the

demultiplexer. The descrambler converts the MB/MB

signal to the transport_error_indicator bit in the TS

packets. At the descrambler output all information is

consequently contained in the stream. MBCLK is only

used to clock data into the descrambler, interfacing to the

demultiplexer is performed using the 9 MHz DCLK, which

is generated by the demultiplexer.

7.6 Boundary scan test

The DVB compliant descrambler is equipped with a 5-pins

test port interface for Boundary Scan Test (BST).

The implementation is in accordance with the BST

standard.

1996 Oct 09

18

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