L4979D 데이터 시트보기 (PDF) - STMicroelectronics

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L4979D

Low drop voltage regulator

STMicroelectronics 

L4979D, L4979MD

Table 10. Reset time diagram

7I

6O

TRR

TR R

6 CR

2ES

Application information

4 OSC

TRD4 OSC

6 OUT?TH

6 RHTH

6RLTH

'!0'#&4

3.3

Watchdog

The watchdog input Wi monitors a connected microcontroller. If pulses are missing, the

reset output Res is set to low. The pulse sequence time can be set within a wide range

through the external capacitor Ctw. The watchdog circuit discharges the capacitor Ctw with

the constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is

generated. To prevent this reset, the microcontroller must generate a positive edge during

the discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to

calculate the minimum time Tdis during which the microcontroller must generate the positive

edge, the following equation can be used:

Vwhth – Vwlth  Ctw = Icwd  Tdis

Each Wi positive edge switches the current source from discharging to charging; the same

happens when the lower Vwlth threshold is reached. When the voltage reaches the upper

threshold Vwhth the current switches from charging to discharging. The result is a saw tooth

voltage at the watchdog timer capacitor Ctw.

Figure 4.

7I

Watchdog time diagram

6CW

TWOL

2ES

4WO P

4DIS

6WHTH

6WLTH

'!0'#&4

Doc ID 10262 Rev 9

11/22

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