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LT3580I

Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization

Linear Technology 

LT3580

APPLICATIONS INFORMATION

Compensation—Theory

Like all other current mode switching regulators, the

LT3580 needs to be compensated for stable and efficient

operation. Two feedback loops are used in the LT3580—

a fast current loop which does not require compensation,

and a slower voltage loop which does. Standard bode plot

analysis can be used to understand and adjust the voltage

feedback loop.

As with any feedback loop, identifying the gain and phase

contribution of the various elements in the loop is critical.

Figure 4 shows the key equivalent elements of a boost

converter. Because of the fast current control loop, the

power stage of the IC, inductor and diode have been replaced

by a combination of the equivalent transconductance

amplifier gmp and the current controlled current source

(which converts IVIN to ηVIN/VOUT • IVIN). gmp acts as

a current source where the peak input current, IVIN, is

proportional to the VC voltage. η is the efficiency of the

switching regulator, and is typically about 88%.

Note that the maximum output currents of gmp and gma are

finite. The limits for gmp are in the Electrical Characteristics

section (switch current limit), and gma is nominally limited

to about ±12μA.

–

gmp

+

VC

gma

CF RC RO

CC

IVIN

H • VIN

VOUT

• IVIN

CPL

1.215V

REFERENCE

R2

FB

R2

VOUT

RESR

RL

COUT

R1

3580 F04

CC: COMPENSATION CAPACITOR

COUT: OUTPUT CAPACITOR

CPL: PHASE LEAD CAPACITOR

CF: HIGH FREQUENCY FILTER CAPACITOR

gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC

gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER

RC: COMPENSATION RESISTOR

RL: OUTPUT RESISTANCE DEFINED AS VOUT DIVIDED BY ILOAD(MAX)

RO: OUTPUT RESISTANCE OF gma

R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK

RESR: OUTPUT CAPACITOR ESR

Figure 4. Boost Converter Equivalent Model

From Figure 4, the DC gain, poles and zeros can be cal-

culated as follows:

Output Pole: P1=

2

2 • π • RL • COUT

Error Amp Pole: P2 =

1

2 • π • ⎡⎣RO + RC ⎤⎦ • CC

Error Amp Zero: Z1=

1

2 • π • RC • CC

DC Gain:

(Breaking Loop at FB Pin)

ADC

= AOL(0) =

∂VC

∂VFB

• ∂IVIN

∂VC

• ∂VOUT

∂IVIN

• ∂VFB

∂VOUT

=

) (gma • R0

• gmp

•

⎛

⎝⎜ η •

VIN

VOUT

•

RL

2

⎞

⎠⎟

•

0.5R2

R1+ 0.5R2

ESR Zero: Z2 =

1

2 • π • RESR • COUT

RHP Zero:

Z3

=

2

•

VIN2 • RL

π • VOUT2

•

L

High Frequency Pole: P3 > fS

3

Phase Lead Zero: Z4 =

1

2 • π • R1• CPL

Phase Lead Pole: P4 =

1

R1• R2

2

•

π

•

R1+

2

R2

• CPL

2

Error Amp Filter Pole:

P5

=

1

2 • π • RC •RO

RC +RO

• CF

,CF

< CC

10

The current mode zero (Z3) is a right-half plane zero

which can be an issue in feedback control design, but is

manageable with proper external component selection.

3580fg

11

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