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LT5521 데이터 시트보기 (PDF) - Linear Technology

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LT5521
Linear
Linear Technology Linear
LT5521 Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
APPLICATIO S I FOR ATIO
LT5521
Figure 17. Top View of Demo Board
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
4.35 ± 0.05 2.15 ± 0.05
(4 SIDES)
2.90 ± 0.05
0.72 ±0.05
4.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 6)
0.75 ± 0.05
2.15 ± 0.10
(4-SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
15 16
0.55 ± 0.20
1
2
PACKAGE
OUTLINE
0.30 ±0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
(UF) QFN 1103
0.30 ± 0.05
0.65 BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5521f
15

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