IS61VPD51236-200TQI 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61VPD51236-200TQI

512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61VPD51232 IS61VPD51236 IS61VPD10018

ISSI ®

IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)

The IS61VF51236 and IS61VF10018 have a serial bound-

ary scan Test Access Port (TAP) in the PBGA package

only. (Not available in TQFP package or with the

IS61VF51232.) This port operates in accordance with

IEEE Standard 1149.1-1900, but does not include all

functions required for full 1149.1 compliance. These

functions from the IEEE specification are excluded because

they place added delay in the critical speed path of the

SRAM. The TAP controller operates in a manner that does

not conflict with the performance of other devices using

1149.1 fully compliant TAPs. The TAP operates using

JEDEC standard 2.5V I/O logic levels.

DISABLING THE JTAG FEATURE

The SRAM can operate without using the JTAG feature.

To disable the TAP controller, TCK must be tied LOW

(GND) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be disconnected. They may

alternately be connected to VCC through a pull-up resistor.

TDO should be left disconnected. On power-up, the

device will start in a reset state which will not interfere with

the device operation.

TEST ACCESS PORT (TAP) - TEST CLOCK

The test clock is only used with the TAP controller. All

inputs are captured on the rising edge of TCK and outputs

are driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to send commands to the TAP

controller and is sampled on the rising edge of TCK. This

pin may be left disconnected if the TAP is not used. The

pin is internally pulled up, resulting in a logic HIGH level.

TEST DATA-IN (TDI)

The TDI pin is used to serially input information to the

registers and can be connected to the input of any

register. The register between TDI and TDO is chosen by

the instruction loaded into the TAP instruction register.

For information on instruction register loading, see the

TAP Controller State Diagram. TDI is internally pulled up

and can be disconnected if the TAP is unused in an

application. TDI is connected to the Most Significant Bit

(MSB) on any register.

TAP CONTROLLER BLOCK DIAGRAM

0

Bypass Register

210

Instruction Register

TDI

Selection Circuitry

. . . 31 30 29

210

Identification Register

x.....210

Boundary Scan Register*

Selection Circuitry TDO

TCK TAP CONTROLLER

TMS

16

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION Rev. 00B

09/25/01

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