M50FW040K5P 데이터 시트보기 (PDF) - STMicroelectronics

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M50FW040K5P

4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory

STMicroelectronics 

Signal descriptions

M50FW040

2.1.10

2.1.11

Write Protect (WP)

The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being

changed. When Write Protect, WP, is set Low, VIL, Program and Erase operations in the

Main Blocks have no effect, regardless of the state of the Lock Register. When Write

Protect, WP, is set High, VIH, the protection of the Block determined by the Lock Register.

The state of Write Protect, WP, does not affect the protection of the Top Block (Block 7).

Write Protect, WP, must be set prior to a Program or Erase operation is initiated and must

not be changed until the operation completes or unpredictable results may occur. Care

should be taken to avoid unpredictable behavior by changing WP during Program or Erase

Suspend.

Reserved for future use (RFU)

These pins do not have assigned functions in this revision of the part. They must be left

disconnected.

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

Address/Address multiplexed (A/A Mux) signal descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see <Blue>Figure 1., Logic

diagram (FWH interface), and <Blue>Table 1., Signal names (FWH interface).

Address inputs (A0-A10)

The Address Inputs are used to set the Row Address bits (A0-A10) and the Column

Address bits (A11-A18). They are latched during any bus operation by the Row/Column

Address Select input, RC.

Data Inputs/Outputs (DQ0-DQ7)

The Data Inputs/Outputs hold the data that is written to or read from the memory. They

output the data stored at the selected address during a Bus Read operation. During Bus

Write operations they represent the commands sent to the Command Interface of the

internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write

operation.

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

Row/Column Address Select (RC)

The Row/Column Address Select input selects whether the Address Inputs should be

latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The

Row Address bits are latched on the falling edge of RC whereas the Column Address bits

are latched on the rising edge.

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