M50FW040K5P 데이터 시트보기 (PDF) - STMicroelectronics
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M50FW040K5P Datasheet PDF : 53 Pages
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Bus operations
M50FW040
Table 4. FWH bus Read field definitions
Clock Clock
Cycle Cycle
Number Count
Field
FWH0- Memory
FWH3 I/O
Description
On the rising edge of CLK with FWH4 Low, the
1
1 START 1101b
I contents of FWH0-FWH3 indicate the start of a FWH
Read cycle.
Indicates which FWH Flash Memory is selected. The
2
1 IDSEL XXXX
I
value on FWH0-FWH3 is compared to the IDSEL
strapping on the FWH Flash Memory pins to select
which FWH Flash Memory is being addressed.
3-9
7 ADDR XXXX
I
A 28-bit address phase is transferred starting with
the most significant nibble first.
10
1 MSIZE 0000b
I
Always 0000b (only single byte transfers are
supported).
11
1
TAR 1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
12
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-
FWH3 during this cycle.
13-14
15
2
WSYN
C
0101b
1
RSYN
C
0000b
The FWH Flash Memory drives FWH0-FWH3 to
O
0101b (short wait-sync) for two clock cycles,
indicating that the data is not yet available. Two wait-
states are always included.
The FWH Flash Memory drives FWH0-FWH3 to
O 0000b, indicating that data will be available during
the next clock cycle.
16-17
2 DATA XXXX
O
Data transfer is two CLK cycles, starting with the
least significant nibble.
18
1
TAR 1111b
O
The FWH Flash Memory drives FWH0-FWH3 to
1111b to indicate a turnaround cycle.
19
1
1111b
TAR
(float)
N/A
The FWH Flash Memory floats its outputs, the host
takes control of FWH0-FWH3.
Figure 6. FWH Bus Read waveforms
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
1
IDSEL
1
ADDR
7
MSIZE
1
TAR
2
SYNC
3
DATA
2
TAR
2
AI03437
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