MAX492 데이터 시트보기 (PDF) - Maxim Integrated

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MAX492

Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op Amps

Maxim Integrated 

Single/Dual/Quad, Micropower,

Single-Supply Rail-to-Rail Op Amps

the op amp in an inverting configuration (Figure 3a);

connect resistor R3 between the noninverting input and

the input signal when using the op amp in a noninvert-

ing configuration (Figure 3b). Select R3 to equal the

parallel combination of R1 and R2. High source resis-

tances will degrade noise performance, due to the ther-

mal noise of the resistor and the input current noise

(which is multiplied by the source resistance).

Input Stage Protection Circuitry

The MAX492/MAX494/MAX495 include internal protec-

tion circuitry that prevents damage to the precision

input stage from large differential input voltages. This

protection circuitry consists of back-to-back diodes

between IN+ and IN- with two 1.7kΩ resistors in series

(Figure 4). The diodes limit the differential voltage

applied to the amplifiers’ internal circuitry to no more

than VF, where VF is the diodes’ forward-voltage drop

(about 0.7V at +25°C).

Input bias current for the ICs (±25nA typical) is speci-

fied for the small differential input voltages. For large

differential input voltages (exceeding VF), this protec-

tion circuitry increases the input current at IN+ and IN-:

(VIN+ - VIN- ) - VF

Input Current = ———————————

2 x 1.7kΩ

For comparator applications requiring large differential

voltages (greater than VF), you can limit the input cur-

rent that flows through the diodes with external resistors

R1

VIN

R2

MAX49_

VOUT

R3

R3 = R2 II R1

MAX492

MAX494

1.7kΩ

TO INTERNAL

MAX495

IN+

CIRCUITRY

IN–

1.7kΩ

TO INTERNAL

CIRCUITRY

Figure 3a. Reducing Offset Error Due to Bias Current:

Inverting Configuration

Figure 4. Input Stage Protection Circuitry

R3

VIN

R3 = R2 II R1

MAX49_

VOUT

R2

10,000

1000

UNSTABLE REGION

R1

VCC = +5V

VOUT = VCC/2

RL TO VEE

AV = +1

100

1

10

100

RESISTIVE LOAD (kΩ)

Figure 3b. Reducing Offset Error Due to Bias Current:

Noninverting Configuration

Figure 5. Capacitive-Load Stable Region Sourcing Current

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