¡ Semiconductor
FEDL9005-03
MSM9005-xx
Input Display Data Configuration
Command
1 CG ROM code data
2 Arbitrator display data
MSB
Input data
LSB
D7 D6 D5 D4 D3 D2 D1 D0
Comment
C7 C6 C5 C4 C3 C2 C1 C0 C0 to C7: CG ROM address
Relationship between AB0 to AB4 and
* * * AB4 AB3 AB2 AB1 AB0 segments pins is as follows.
S5n+1
S5n+5
3 Arbitrator blink data
*: Don't care
* * * AB4 AB3 AB2 AB1 AB0
AB4
AB0
n = 0 to 12
Output Display Data Configuration
Command
1 CG ROM code data
2 Arbitrator display data
MSB
Input data
LSB
D7 D6 D5 D4 D3 D2 D1 D0
Comment
C7 C6 C5 C4 C3 C2 C1 C0 C0 to C7: CG ROM address
Relationship between RD0 to RD4 and
segment pins is as follows.
0 0 0 RD4 RD3 RD2 RD1 RD0
S5n+1
S5n+5
RD4
RD0
n = 0 to 12
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