MT46H16M16 데이터 시트보기 (PDF) - Micron Technology

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MT46H16M16

Mobile DDR SDRAM

Micron Technology 

256Mb: x16, x32 Mobile DDR SDRAM

General Description

The 256Mb Mobile DDR SDRAM operates from a differential clock (CK and CK#); the

crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of

CK. Commands (address and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at

a selected location and continue for a programmed number of locations in a

programmed sequence. Accesses begin with the registration of an ACTIVE command,

which is then followed by a READ or WRITE command. The address bits registered coin-

cident with the ACTIVE command are used to select the bank and row to be accessed.

The address bits registered coincident with the READ or WRITE command are used to

select the bank and the starting column location for the burst access.

The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,

4, or 8. An auto precharge function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access.

As with standard SDR SDRAM, the pipelined, multibank architecture of Mobile DDR

SDRAM enables concurrent operation, thereby providing high effective bandwidth by

hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-saving power-down mode. Deep

power-down mode is offered to achieve maximum power reduction by eliminating the

power draw of the memory array. Data will not be retained when the device enters DPD

mode.

Notes:

Self refresh mode offers temperature compensation through an on-chip temperature

sensor and partial-array self refresh, which enables users to achieve additional power

savings. The temperature sensor is enabled by default, and the partial-array self refresh

can be programmed through the extended mode register.

1. Throughout the data sheet, various figures and text refer to DQs as “DQ.” The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated oth-

erwise.

2. Complete functionality is described throughout the document, and any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all

requirements.

3. Any specific requirement takes precedence over a general statement.

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__2.fm - Rev. H 6/08 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2005 Micron Technology, Inc. All rights reserved.

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