HI7188(2000) 데이터 시트보기 (PDF) - Intersil
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HI7188 Datasheet PDF : 24 Pages
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(RESET) INITIAL SYSTEM START
PROGRAM THE SYSTEM LEVEL
INFORMATION IN THE
CONTROL REGISTER (CR)
APPLY A ZERO SCALE INPUT
TO EACH OF THE CHANNELS
PROGRAM THE CHANNEL LEVEL
INFORMATION IN THE
CHANNEL CONFIGURATION
REGISTERS (CCR)
AND PLACE EACH CHANNEL
IN OFFSET CALIBRATION MODE
YES
CA OUTPUT
INTERRUPT ACTIVE?
NO
APPLY A POSITIVE FULL SCALE INPUT
TO EACH CHANNEL
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
POSITIVE FULL SCALE
CALIBRATION MODE
YES
CA OUTPUT
INTERRUPT ACTIVE?
NO
APPLY A NEGATIVE FULL SCALE
INPUT TO EACH CHANNEL
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
NEGATIVE FULL SCALE
CALIBRATION MODE
YES
CA OUTPUT
INTERRUPT ACTIVE?
NO
CONNECT DESIRED ANALOG INPUT,
READ DATA RAM VIA
SERIAL INTERFACE
NO
EOS OUTPUT
INTERRUPT ACTIVE?
YES
NO
RECALIBRATION REQUIRED?
YES
FIGURE 7. SYSTEM USAGE FLOWCHART
11
HI7188
PHYSICAL
CHANNELS
REFERENCE INPUTS
VIN1H
VIN2H
VIN3H
VIN4H
VIN5H
VIN6H
VIN7H
VIN8H
VCM
VRHI VRLO
VIN1L
VIN2L
VIN3L
VIN4L
VIN5L
VIN6L
VIN7L
VIN8L
PGIA
4TH
ORDER
∑−∆
MODULATOR
DIGITAL
SECTION
CONVERSION
CONTROL
FIGURE 8. ANALOG BLOCK DIAGRAM
The configuration can be saved by writing the contents of the
CR, CCR and calibration RAMs to microprocessor system
memory (see Serial Interface section). After this has
occurred, the configuration can easily be restored back to
the HI7188 in the event of power failure or reset.
Analog Section Description
The analog portion of the HI7188 consists of a 8 to 1 fully
differential Multiplexer, Programmable Gain Instrumentation
amplifier (PGIA) and a 4th order Sigma-Delta modulator.
Please refer to the simplified analog block diagram in Figure 8.
Analog Inputs
The analog inputs on the HI7188 are fully differential inputs
with programmable gain capabilities. The inputs accept both
unipolar and bipolar input signals and gains of 1, 2, 4 or 8.
The gain for any given physical channel is independent of
the gain of other physical channels. The gain is programmed
via the Channel Configuration Register (CCR).
The input impedance of the HI7188 is dependent upon the
modulator input sampling capacitors which varies with the
selected PGIA gain. Table 2 shows the sampling capacitors
and input impedances for the different gain settings of the
HI7188. Note that this table is valid only for a 3.6864MHz
master clock. If the input clock frequency is changed then
the input impedance will change accordingly. The equation
used to calculate the input impedance is
ZIN = 1/(CS x FS)
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