S3C8625 데이터 시트보기 (PDF) - Samsung
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S3C8625 Datasheet PDF : 24 Pages
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PRODUCT OVERVIEW
S3C8625/C8627/C8629/P8629
PIN DESCRIPTIONS
Table 1-1. S3C8625/C8627/C8629/P8629 Pin Descriptions
Pin
Names
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
Pin
Type
Pin
Description
I/O General-purpose, 8-bit I/O port. Shared
functions include three external interrupt
inputs and I/O for timer M0 and M1.
Selective configuration of port 0 pins to
input or output mode is supported.
I/O General-purpose, 3-bit I/O port. Selective
configuration is available for port 1 pins to
input, push-pull output, n-channel open-
drain mode, or IIC-bus clock and data I/O.
Circuit
Type
D-1
D-1
D-1
D-1
D-1
D-1
D-1
D-1
E-1
E-1
E-1
SDIP Pin
Numbers
1
2
3
4
5
6
7
8
9
10
19
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
I/O General-purpose, 8-bit I/O port Selective
D-1
configuration of port 2 pins to input or
D-1
output mode is supported. The port 2 pin
D-1
circuits are designed to push-pull PWM
D-1
output and Csync signal input.
E-1
E-1
E-1
D-1
P3.0–P3.3
I/O General-purpose, 8-bit I/O port Selective
D-1
P3.4–P3.7
configuration port 3 pins to input or output
E
mode is supported. Multiplexed for
alternative use as A/D converter inputs
AD0–AD3.
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
SCL0
I The pins are sync processor signal I/O, IIC-
A
I bus clock, and data I/O.
A
O
A
O
A
O
A
I/O
G-3
I/O
G-3
VDD, VSS1,
– Power pins
–
AVREF, VSS2
ADC power pins
–
XIN, XOUT
– System clock I/O pins
–
RESET
I System reset pin
B
TEST
I Factory test pin input
–
0V:Normal operation,5V:Factory test mode
20
21
22
23
24
25
26
32
35–38,
39–42
31
30
27
28
29
16
17
11, 12
34, 33
14, 13
18
15
Shared
Functions
INT0
INT1
INT2
TM0CAP
TM1CK
SDA1
SCL1
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
AD0–AD3
–
–
–
–
–
1-6
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