W88111AF 데이터 시트보기 (PDF) - Winbond

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W88111AF

ATAPI CD-ROM Decoder & Controller

Winbond 

W88111AF/W88112F

ATAPI CD-ROM Decoder & Controller

This specification is subject to change without notice.

Bits 4, 3, 2: Reserved

Preliminary/Confidential

Bit 1: DTEN - Data Transfer Enable

Set DTEN high enables the data transfer logic. This bit should be set before any of the following

data transfers is triggered:

• Host write to the Packet FIFO

• Host read from external RAM

• Host read from DF0 to DF7

In order to reduce the interference of microprocessor, DTEN is also automatically enabled during

the following operation:

• Trigger ADTT(17h.2)

• Host issues ATAPI Packet Command(A0h) while APKTEN(18h.7) is enabled and drive is

selected

Bit 0: Reserved

INTREA - Interrupt Reason Register - (read 01h)

Bit 7: PFNEb - Packet FIFO Not Empty Interrupt Flag

This bit becomes active-low after Packet FIFO receives any data issued by the host through

ATAPI Data port. UINTb(pin 36) is activated when PFNEb becomes active-low if PFNEEN(01h.7)

is enabled. PFNEb is deactivated after the last byte is read by microprocessor through register

PFAR(00h).

Bit 6: TENDb - Transfer End Interrupt Flag

This bit becomes active-low at the end of the following data transfers:

• Host writes to the Packet FIFO

• Host read from external RAM

• Host read from registers DF0(40h) to DF7(47h)

Flags TDIR(30h.5) and FPKT(30h.1) can be used to determine which type of transfer end occurs.

UINTb(pin36) is activated when TENDb becomes active-low if TENDEN(01h.6) is enabled.

Writing any value to register TACK(07h) deactivates this flag.

Bit 5: SRIb - Sector Ready Interrupt Flag

This bit is used to indicate that one sector is ready to be accessed. Reading register STAT3(0Fh)

deactivates SRIb.

- 13 -

Publication Release Date: Aug, 1996

Preliminary/ Confidential Revision A0.1

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